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    Strained silicon MOSFET having reduced leakage and method of its formation
    42.
    发明授权
    Strained silicon MOSFET having reduced leakage and method of its formation 有权
    应变硅MOSFET具有减少的泄漏和其形成方法

    公开(公告)号：US06924182B1

    公开(公告)日：2005-08-02

    申请号：US10642375

    申请日：2003-08-15

    Applicant: Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    Inventor： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/76

    CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

    Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

    Abstract translation: 应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。 选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率 在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。 随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。 这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

    Offset spacer process for forming N-type transistors
    43.
    发明授权
    Offset spacer process for forming N-type transistors 有权
    用于形成N型晶体管的偏置间隔工艺

    公开(公告)号：US06905923B1

    公开(公告)日：2005-06-14

    申请号：US10619877

    申请日：2003-07-15

    Applicant: Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    Inventor： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864

    Abstract: A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.

    Abstract translation: 制造具有源极和漏极结的SMOS集成电路的方法利用用于N型晶体管的偏移栅极间隔物。 植入离子以形成应变层中的源区和漏区。 偏移间隔物减少了在应变半导体层上与砷（As）扩散相关的问题。 该工艺可用于SMOS金属氧化物半导体场效应晶体管（MOSFET）。 应变层可以是形成在锗层之上的应变硅层。

    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
    46.
    发明授权
    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
    形成厚应变硅层的方法和掺入厚应变硅层的半导体结构

    公开(公告)号：US06730576B1

    公开(公告)日：2004-05-04

    申请号：US10335447

    申请日：2002-12-31

    Applicant: Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    Inventor： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    IPC: H01L21762

    CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    Abstract: A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

    Abstract translation: 应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。 在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。 两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。 因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。 在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

    Method and apparatus for chemical polishing using field responsive materials
    47.
    发明授权
    Method and apparatus for chemical polishing using field responsive materials 有权
    使用场响应材料进行化学抛光的方法和装置

    公开(公告)号：US06297159B1

    公开(公告)日：2001-10-02

    申请号：US09350975

    申请日：1999-07-07

    Applicant: Eric N. Paton

    Inventor： Eric N. Paton

    IPC: H01L21302

    CPC classification number: H01F1/447 ,  B24B1/005 ,  B24B37/04 ,  H01L21/3212

    Abstract: A process for, and apparatus for, Chemically-Mechanically Polishing (CMP) a semiconductor wafer with a slurry including ElectroRheological (ER) and/or MagnetoRheological (MR) fluids. The combination of the materials and an electric field provides inherent tuning of polishing rates, locally and globally, and improves flatness and uniformity, as well as minimizing recession and erosion.

    Abstract translation: 用包括电流变（ER）和/或磁流变（MR）流体的浆料在内的化学机械抛光（CMP）半导体晶片的方法和装置。 材料和电场的组合提供了本地和全球抛光速率的固有调谐，并且改善了平整度和均匀性，并且使衰退和侵蚀最小化。

    Method and apparatus for controlling the thickness of a selective epitaxial growth layer
    50.
    发明授权
    Method and apparatus for controlling the thickness of a selective epitaxial growth layer 有权
    用于控制选择性外延生长层厚度的方法和装置

    公开(公告)号：US07402207B1

    公开(公告)日：2008-07-22

    申请号：US10839378

    申请日：2004-05-05

    Applicant: Paul R. Besser ,  Eric N. Paton ,  William G. En

    Inventor： Paul R. Besser ,  Eric N. Paton ,  William G. En

    IPC: C30B21/04

    CPC classification number: C30B25/16 ,  G01B11/0616 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745 ,  Y10T117/1004 ,  Y10T117/1008

    Abstract: Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.

    Abstract translation: 提出了在半导体制造工艺中允许厚度控制选择性外延生长（SEG）层的方法和系统，例如CMOS技术中的升高的源/漏应用。 这些方法和系统提供了在从SEG生长工具移除晶片之前在SEG层生长期间或之后使用光学椭偏仪设备原位测量SEG膜的厚度的能力。 光学椭圆测量设备可以集成到SEG平台和控制软件中，从而为SEG厚度提供自动化过程控制（APC）能力。 椭圆测量设备的集成可以根据制造设施的需要而变化，例如集成以提供单个处理工具的椭偏仪监控，或者多个工具监视以及其他配置。

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