公开(公告)号：US20100107403A1

公开(公告)日：2010-05-06

申请号：US12579654

申请日：2009-10-15

申请人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

发明人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

IPC分类号： H01H69/02

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

摘要： In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

摘要翻译： 在复杂的集成电路中，可以形成电子熔断器，使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成相应的熔丝区域作为非线性配置来实现，其中在对应的线性段的连接部分期间，在施加编程电压期间可能发生所需的增强的电流拥挤。 因此，可以实现电子熔断器的增加的可靠性和更节省空间的布局。

公开(公告)号：US20100078645A1

公开(公告)日：2010-04-01

申请号：US12553475

申请日：2009-09-03

申请人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

发明人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L27/06

CPC分类号： H01L27/0629 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/20

摘要： An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

摘要翻译： 嵌入或埋入的电阻结构可以通过半导体材料的非晶化并随后在多晶态中重新结晶而形成，从而提供与诸如多晶硅电阻器的常规多晶电阻器的高度兼容性，同时避免专用 多晶材料。 因此，多晶电阻器可以有利地与基于非硅栅电极材料的复杂晶体管架构组合，同时还提供相对于寄生电容的电阻器的高性能。

公开(公告)号：US20090057813A1

公开(公告)日：2009-03-05

申请号：US12052202

申请日：2008-03-20

申请人： Andy Wei ,  Roman Boschke ,  Markus Forsberg

发明人： Andy Wei ,  Roman Boschke ,  Markus Forsberg

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

摘要： By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

摘要翻译： 通过在提供高k电介质层堆叠之后形成沟槽隔离结构，可以避免沟槽隔离结构的顶表面中的含氧绝缘材料与共享折线中的高k电介质材料的直接接触。 这种技术是自对准的，从而能够进一步进行器件定标，而不需要非常严格的光刻公差。 在形成沟槽隔离结构之后，可以通过提供另外的导电材料来重新建立穿过沟槽隔离结构的期望的电连接。

公开(公告)号：US20090001371A1

公开(公告)日：2009-01-01

申请号：US12026273

申请日：2008-02-05

申请人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

发明人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.

摘要翻译： 提出了一种技术，其提供晶体管的源极/漏极区域的选择性预非晶化，同时防止晶体管的栅电极的前非晶化。 示例性实施例包括在栅电极上形成预非晶化注入阻挡材料。 进一步的说明性实施例包括通过使用各种压力源在通道区域中诱导应变。

公开(公告)号：US08722486B2

公开(公告)日：2014-05-13

申请号：US12908053

申请日：2010-10-20

申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

公开(公告)号：US08664049B2

公开(公告)日：2014-03-04

申请号：US12776879

申请日：2010-05-10

申请人： Stephan Kronholz ,  Roman Boschke ,  Vassilios Papageorgiou ,  Maciej Wiatr

发明人： Stephan Kronholz ,  Roman Boschke ,  Vassilios Papageorgiou ,  Maciej Wiatr

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1207 ,  H01L21/823418 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7845 ,  H01L29/7848

摘要： The PN junction of a substrate diode in a sophisticated SOI device may be formed on the basis of an embedded in situ doped semiconductor material, thereby providing superior diode characteristics. For example, a silicon/germanium semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.

摘要翻译： 可以在嵌入式原位掺杂半导体材料的基础上形成复杂SOI器件中的衬底二极管的PN结，从而提供优异的二极管特性。 例如，可以在衬底材料的空腔中形成硅/锗半导体材料，其中可以选择空腔的尺寸和形状以避免与金属硅化物材料的过度相互作用。

公开(公告)号：US08617940B2

公开(公告)日：2013-12-31

申请号：US12639515

申请日：2009-12-16

申请人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

发明人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

IPC分类号： H01L29/66

CPC分类号： H01L27/0629 ,  H01L21/31111 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203

摘要： In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

摘要翻译： 在SOI器件中，电路元件（例如衬底二极管）的PN结基于掩埋绝缘材料形成在衬底材料中，该掩埋绝缘材料在湿化学清洗和蚀刻工艺期间提供增加的蚀刻电阻率。 因此，可以避免在掩埋绝缘材料的侧壁附近形成的PN结的过度曝光，这可能导致包括二氧化硅材料作为掩埋绝缘层的常规SOI器件的可靠性问题。

公开(公告)号：US08609498B2

公开(公告)日：2013-12-17

申请号：US13006148

申请日：2011-01-13

申请人： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

发明人： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC分类号： H01L21/8222

CPC分类号： H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors.

摘要翻译： 在复杂的半导体器件中，可以在晶体学各向异性蚀刻工艺和自限制沉积工艺的基础上提供应变诱导嵌入式半导体合金，其中可能不需要嵌入式应变诱导半导体合金的晶体管可以保持非掩蔽 ，从而在整个晶体管配置方面提供优异的均匀性。 因此，可以在一种类型的晶体管中实现优异的应变条件，而对于任何类型的晶体管，可以获得晶体管特性的一般降低的变化。

公开(公告)号：US08193066B2

公开(公告)日：2012-06-05

申请号：US12477365

申请日：2009-06-03

申请人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

发明人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

IPC分类号： H01L21/20

CPC分类号： H01L27/0802 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20

摘要： In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times.

摘要翻译： 在集成电路中，可以在硅/锗材料的基础上形成电阻器，从而提供降低的电阻率，这可以减小电阻元件的尺寸。 此外，可以使用减少的掺杂剂浓度，其可以允许增加的工艺窗口来调节电阻值，同时还减少总的循环时间。

公开(公告)号：US20110291163A1

公开(公告)日：2011-12-01

申请号：US12965118

申请日：2010-12-10

申请人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

发明人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。