公开(公告)号：US06383872B1

公开(公告)日：2002-05-07

申请号：US09160829

申请日：1998-09-25

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

IPC分类号： H01L21335

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42376 ,  Y10S257/904 ,  Y10S438/947

摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

摘要翻译： 提出了逻辑门内的晶体管的改进的串联和/或并联连接。 改进的连接是通过牺牲结构实现的，在该牺牲结构上，邻近牺牲结构的侧壁表面形成栅极导体。 牺牲结构由此提供串联或并联连接的晶体管之间的间隔。 在去除每个牺牲结构时，可以通过在间隔的导体的相对侧上将掺杂剂物质注入到衬底中来形成一对晶体管。 在一旦牺牲结构之下，就是两个晶体管串联或并联耦合到的共享注入区域。 通过沉积栅极导体材料，然后各向异性除去邻近垂直侧壁表面的材料，可以在逻辑门内与其它栅极导体同时形成超短栅极导体。

公开(公告)号：US06365943B1

公开(公告)日：2002-04-02

申请号：US09157644

申请日：1998-09-21

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

IPC分类号： H01L2976

CPC分类号： H01L21/823437 ,  Y10S438/947

摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

公开(公告)号：US6140163A

公开(公告)日：2000-10-31

申请号：US893744

申请日：1997-07-11

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/822 ,  H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

摘要翻译： 高性能半导体器件结构及其制造方法包括体半导体衬底和上层硅衬底。 上层硅衬底包括低K电介质层和硅衬底层。 低K电介质层形成在体半导体衬底上，低K电介质层的介电K值在2.0-3.8范围内。 然后将硅衬底层和低K电介质层在第一区域中被图案化到上层衬底中，并且在第二区域中暴露体半导体衬底。 栅极氧化物层形成在第一区域中的上层衬底之上并且在第二区域中的暴露的体半导体衬底之上。 最后，晶体管器件形成在上层衬底和体半导体衬底中。

公开(公告)号：US6104064A

公开(公告)日：2000-08-15

申请号：US306508

申请日：1999-05-06

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L29/66659 ,  H01L29/7835

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US6075258A

公开(公告)日：2000-06-13

申请号：US136177

申请日：1998-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/76

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

公开(公告)号：US6069046A

公开(公告)日：2000-05-30

申请号：US979282

申请日：1997-11-26

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/665

摘要： A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the sacrificial layer and an LDD implant self-aligned to exposed lateral edges of sidewall spacers arranged upon the sidewall surfaces of the sacrificial layer are performed. The polysilicon layer is then etched to define a gate conductor above and between LDD areas arranged within the substrate.

摘要翻译： 提供了一种制造晶体管的工艺，其中在限定栅极导体的侧壁表面之前执行掺杂剂到源极/漏极结的离子注入。 因此，栅极导体的侧壁表面不会受到离子的破坏性轰击。 在一个实施例中，掩模层被图案化在介于半导体衬底之上的多晶硅层之上。 执行与掩模层的侧壁表面自对准的S / D注入。 去除掩模层的一部分以减小掩模层的宽度并形成更紧密间隔的侧壁。 执行与掩模层的新侧壁自对准的LDD注入。 此后，蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。 在另一个实施例中，在半导体衬底上介电间隔的多晶硅层上方构图牺牲层。 执行自对准到牺牲层的侧壁表面的S / D注入和与排列在牺牲层的侧壁表面上的侧壁间隔件的暴露的侧向边缘自对准的LDD注入。 然后蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。

公开(公告)号：US6048803A

公开(公告)日：2000-04-11

申请号：US914658

申请日：1997-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/02131 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/31629 ,  H01L21/76801

摘要： A semiconductor device having relatively low permittivity fluorine bearing oxide between conductive lines and a method for fabricating such a device is provided. At least two adjacent conductive lines are formed over a substrate. An oxide layer is formed between the adjacent conductive lines. A mask is formed over the oxide layer and selectively removed to expose a portion of the oxide layer between the adjacent conductive lines. A fluorine bearing species is implanted into the exposed portion of the oxide layer to reduce the permittivity of the oxide layer between the adjacent conductive lines. The permittivity or dielectric constant of the oxide layer between the adjacent conductive lines can, for example, be reduced from about 3.9 to 4.2 to about 3.0 to 3.5.

摘要翻译： 提供了一种在导线之间具有较低介电常数含氟氧化物的半导体器件及其制造方法。 在衬底上形成至少两个相邻的导线。 在相邻的导线之间形成氧化物层。 掩模形成在氧化物层的上方并被选择性地去除以暴露相邻导电线之间的氧化物层的一部分。 将含氟物质注入到氧化物层的暴露部分中以降低相邻导电线之间的氧化物层的介电常数。 相邻导电线之间的氧化物层的介电常数或介电常数例如可以从约3.9至4.2降低至约3.0至3.5。

公开(公告)号：US6037629A

公开(公告)日：2000-03-14

申请号：US28895

申请日：1998-02-24

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。

公开(公告)号：US6027964A

公开(公告)日：2000-02-22

申请号：US905681

申请日：1997-08-04

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/02 ,  H01L21/266 ,  H01L21/336 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L28/20 ,  H01L21/266 ,  H01L27/0629 ,  H01L29/66659

摘要： A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the active region and the resistor region, forming a masking layer over the insulating layer that includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate, applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate so that an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor, and forming a source and a drain in the active region including at least partially doping the source and the drain during a doping step that provides more doping for the first portion of the gate than for the second portion of the gate after forming the masking layer. In this manner, the masking layer can provide both an etch mask for the resistor-protect insulator and an implant mask for selectively doping the gate.

摘要翻译： 制造具有选择性掺杂栅极的IGFET与受保护电阻器组合的方法包括以下步骤：为半导体衬底提供有源区域和电阻器区域，在有源区域上形成栅极，在电阻器区域中形成扩散电阻器 在所述有源区和所述电阻区上方形成绝缘层，在所述绝缘层上形成掩模层，所述绝缘层包括在所述栅极的第一部分上方的开口，并且覆盖所述电阻器区域和所述栅极的第二部分，使用 掩模层作为蚀刻掩模，以去除栅极的第一部分之上的绝缘层，使得绝缘层的未蚀刻部分在栅极的第二部分上形成栅极保护绝缘体，并且形成绝缘层的另一个未蚀刻部分 在所述扩散电阻器上方的电阻保护绝缘体，以及在所述有源区域中形成至少部分掺杂所述酸的源极和漏极 在掺杂步骤中，在形成掩模层之后，栅极的第一部分比栅极的第二部分提供更多的掺杂。 以这种方式，掩模层可以提供用于电阻器保护绝缘体的蚀刻掩模和用于选择性地掺杂栅极的注入掩模。

公开(公告)号：US5970375A

公开(公告)日：1999-10-19

申请号：US851086

申请日：1997-05-03

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/768 ,  H01L21/336

CPC分类号： H01L21/76895

摘要： An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor. Portions of the interlevel dielectric and the local interconnect are removed in sequence while retaining the patterned masking layer. Removal of the local interconnect forms vias extending to the gate conductor of one transistor and to a junction of the other transistor, or from the gate conductor of one transistor to a junction of the same transistor. A conductive material may be deposited in these vias to form plugs therein. Further, a capping dielectric layer may be deposited upon the interlevel dielectric and contact regions may be formed which abut the plugs. Therefore, distal interconnect conductive layers may then be formed dielectrically above the local interconnect which are then electrically coupled to the local interconnect through the contact regions.

摘要翻译： 提供一种集成电路制造工艺，其中在一个晶体管的栅极导体和另一个晶体管的结之间形成子级局部互连。 子级局部互连的形成允许通过将本地互连移除到与可能的其它本地互连以及通常与设备互连相关联的远端互连的介电间隔的子级别来实现更高的堆叠密度。 提供半导体形貌，其包括与第二晶体管横向隔开的第一晶体管，晶体管布置在衬底上和衬底内。 跨越半导体形貌沉积层间电介质。 去除层间电介质的一部分以形成沟槽。 然后用导电材料填充沟槽，以形成在第一晶体管的一部分和第二晶体管的一部分上方水平延伸的局部互连。 层叠电介质和局部互连的部分在保持图案化掩模层的同时被顺序地去除。 去除局部互连形成延伸到一个晶体管的栅极导体和另一个晶体管的结或从一个晶体管的栅极导体到同一晶体管的结的结的通孔。 导电材料可以沉积在这些通孔中以在其中形成插塞。 此外，可以在层间电介质上沉积覆盖电介质层，并且可以形成接触插塞的接触区域。 因此，远端互连导电层然后可以介电地形成在局部互连上方，然后电连接到局部互连通过接触区域。