公开(公告)号：US20170338313A1

公开(公告)日：2017-11-23

申请号：US15595611

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170338300A1

公开(公告)日：2017-11-23

申请号：US15595717

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/745 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170278924A1

公开(公告)日：2017-09-28

申请号：US15077579

申请日：2016-03-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/808 ,  H01L29/73 ,  H01L29/78 ,  H01L29/16 ,  H01L29/861

CPC classification number: H01L29/0634 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66272 ,  H01L29/66909 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US20160380059A1

公开(公告)日：2016-12-29

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

Abstract translation: 本文公开的主题涉及碳化硅（SiC）功率器件，更具体地，涉及用于SiC超结（SJ）功率器件的有源区域设计。 SiC-SJ器件包括具有一个或多个电荷平衡（CB）层的有源区。 每个CB层包括具有第一导电类型的半导体层和设置在半导体层的表面中的具有第二导电类型的多个浮动区域。 当将反向偏压施加到SiC-SJ器件时，多个浮动区域和半导体层都被配置为基本上耗尽以提供基本相等量的电离掺杂剂的电荷。

公开(公告)号：US12191384B2

公开(公告)日：2025-01-07

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11031472B2

公开(公告)日：2021-06-08

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US20200212182A1

公开(公告)日：2020-07-02

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US10608079B2

公开(公告)日：2020-03-31

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L27/092 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/761 ,  H01L21/82 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US10600649B2

公开(公告)日：2020-03-24

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10586846B2

公开(公告)日：2020-03-10

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.