公开(公告)号：US20180190791A1

公开(公告)日：2018-07-05

申请号：US15398489

申请日：2017-01-04

Applicant: General Electric Company

Inventor： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7424 ,  H01L29/7811 ,  H01L29/8618

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US10002920B1

公开(公告)日：2018-06-19

申请号：US15379214

申请日：2016-12-14

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US09735237B2

公开(公告)日：2017-08-15

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/872 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

公开(公告)号：US09230807B2

公开(公告)日：2016-01-05

申请号：US13718031

申请日：2012-12-18

Applicant: General Electric Company

Inventor： Zachary Matthew Stum ,  Reza Ghandi

IPC: H01L21/02 ,  H01L21/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L21/02697 ,  H01L21/0485 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L23/5226 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/808 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Abstract translation: 提出了一种碳化硅器件，其包括设置在碳化硅衬底的一部分上的栅电极以及设置在栅电极上的电介质膜。 该器件具有设置在栅电极附近的接触区域，并且具有设置在电介质膜上方并且在接触区域上方的层。 该层包括设置在电介质膜上的部分的镍，并且包括设置在接触区域上的部分的硅化镍。 镍硅化物层被配置为向碳化硅器件的接触区域提供欧姆接触。

公开(公告)号：US20240038836A1

公开(公告)日：2024-02-01

申请号：US17878655

申请日：2022-08-01

Applicant: General Electric Company

Inventor： Collin William Hitchcock ,  Reza Ghandi

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/266 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/0634 ,  H01L29/7813 ,  H01L29/0696 ,  H01L21/266 ,  H01L29/66712 ,  H01L29/1608

Abstract: A semiconductor device includes a first epitaxial (epi) layer that forms a first super-junction (SJ) layer of the semiconductor device and a second epi layer disposed on the first SJ layer that forms a device layer of the semiconductor device. The first epi layer includes oppositely doped SJ pillars that extend along a first direction within the SJ layer. The device layer includes device structures of a striped metal-oxide-semiconductor field-effect transistor (MOSFET) device cell that extends along a second direction within the device layer. The angle between the first direction and the second direction is substantially between forty-five degrees and ninety degrees, inclusive.

公开(公告)号：US11482449B2

公开(公告)日：2022-10-25

申请号：US16983380

申请日：2020-08-03

Applicant: General Electric Company

Inventor： Cheng-Po Chen ,  Reza Ghandi ,  David Richard Esler ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Liang Yin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/02 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532

Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

公开(公告)号：US11233157B2

公开(公告)日：2022-01-25

申请号：US16147210

申请日：2018-09-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/812 ,  H01L29/80 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16

Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

公开(公告)号：US20150276686A1

公开(公告)日：2015-10-01

申请号：US14225768

申请日：2014-03-26

Applicant: General Electric Company

Inventor： William Albert Challener ,  Sachin Narahari Dekate ,  Sabarni Palit ,  Ansas Matthias Kasten ,  Reza Ghandi

IPC: G01N29/42 ,  G01N29/24 ,  E21B47/06 ,  B81B7/02

CPC classification number: G01N29/42 ,  B81B7/02 ,  E21B47/06 ,  G01D5/266 ,  G01D5/285 ,  G01L9/0011 ,  G01N29/2418 ,  G01N2291/014 ,  G01N2291/02872 ,  G01N2291/02881

Abstract: A sensor interrogation unit in one embodiment includes a control module, a reading module, and a determination module. The control module is configured to control one or more lasers to provide a pulsed signal to at least one sensor. Each period of the pulsed signal has a first component having a first intensity and a second component having a second intensity that is lower than the first intensity. The reading module is configured to receive at least one return signal comprising reflections of the pulsed signal from the at least one sensor, to read one of the first component or the second component, and to provide frequency information based on the read reflections. The determination module is configured to determine at least one resonant frequency of the at least one sensor based on the frequency information.

Abstract translation: 一个实施例中的传感器询问单元包括控制模块，读取模块和确定模块。 控制模块被配置为控制一个或多个激光器以向至少一个传感器提供脉冲信号。 脉冲信号的每个周期具有具有第一强度的第一分量和具有低于第一强度的第二强度的第二分量。 读取模块被配置为接收包括来自至少一个传感器的脉冲信号的反射的至少一个返回信号，以读取第一部件或第二部件中的一个，并且基于读取的反射来提供频率信息。 确定模块被配置为基于频率信息来确定至少一个传感器的至少一个谐振频率。

公开(公告)号：US12125745B2

公开(公告)日：2024-10-22

申请号：US17949325

申请日：2022-09-21

Applicant: General Electric Company

Inventor： Cheng-Po Chen ,  Reza Ghandi ,  David Richard Esler ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Liang Yin

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/02172 ,  H01L23/3192 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05599 ,  H01L2924/1904

Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

公开(公告)号：US20220130953A1

公开(公告)日：2022-04-28

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.