公开(公告)号：US20160133623A1

公开(公告)日：2016-05-12

申请号：US14536243

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Andre Labonte ,  Su Chen Fan ,  Balasubramanian S. Pranatharthi Haran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.

Abstract translation: 本文公开的一种方法包括在凹陷的最终栅极结构上方和在凹陷的侧壁间隔物之上形成栅极盖层，形成导电耦合到第一源极/漏极区域的凹陷沟槽硅化物区域，凹陷沟槽硅化物区域 具有位于所述侧壁间隔物的凹陷的上表面下方的水平面的上表面，在暴露所述凹入的最终栅极结构的导电部分的至少一层材料中形成组合的接触开口， 沟槽硅化物区域，并且在组合的接触开口中形成组合的栅极和源极/漏极接触结构。

公开(公告)号：US20160118385A1

公开(公告)日：2016-04-28

申请号：US14981574

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure, wherein an internal sidewall surface of each of the spaced-apart sidewall spacers has a stepped cross-sectional configuration

Abstract translation: 晶体管器件包括位于半导体衬底上方的栅极结构和位于衬底上方的间隔开的侧壁隔离物和栅极结构的相邻侧壁，其中每个间隔开的侧壁间隔件的内侧壁表面具有阶梯状横截面 组态

公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract translation: 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。