公开(公告)号：US20180069092A1

公开(公告)日：2018-03-08

申请号：US15258333

申请日：2016-09-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20170104011A1

公开(公告)日：2017-04-13

申请号：US14878332

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/8234 ,  H01L21/84

Abstract: Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with SOI devices. The SOI initially covers the entire substrate and is then removed from the bulk device region. The bulk device region has a thicker dielectric on the substrate than the SOI region. The regions are separated by isolation material, and may or may not be co-planar.

公开(公告)号：US20170069759A1

公开(公告)日：2017-03-09

申请号：US14847462

申请日：2015-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7853 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/66818

Abstract: A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping, after removal of the dummy gate and before a replacement metal gate is formed.

Abstract translation: 三维晶体管包括在去除伪栅极之后并且在替换金属栅极形成之前具有去除中心部分（叉形沟道）或侧部（窄沟道）或不形成的鳍的沟道。

公开(公告)号：US20160300922A1

公开(公告)日：2016-10-13

申请号：US14681428

申请日：2015-04-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213

CPC classification number: G01P15/00 ,  G01C22/006 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.

Abstract translation: 半导体器件和用于形成具有间隔物倒角的器件的方法。 一种方法包括例如：获得具有至少一个源的晶片，至少一个漏极和至少一个鳍片; 用至少一个阻挡层形成至少一个牺牲栅极; 形成邻近所述至少一个牺牲栅极的第一组间隔件; 形成邻近所述第一组间隔物的至少一个第二组间隔件; 以及蚀刻以去除所述至少一个阻挡层上方的所述第一组隔离物的一部分以形成加宽的开口。 还公开了一种中间半导体器件。

公开(公告)号：US20160276350A1

公开(公告)日：2016-09-22

申请号：US14662734

申请日：2015-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

Abstract translation: 半导体结构包括半导体衬底，n型或p型的至少一个第一细长区域和n型或p型另一个的至少一个另外的第二细长区域，第一和第二细长区域跨越 使得第一细长区域和第二细长区域在公共区域相交，并且在每个公共区域上共享门结构。

公开(公告)号：US20160254180A1

公开(公告)日：2016-09-01

申请号：US14633341

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu LIU ,  Hui ZANG

IPC: H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649

Abstract: A method as set forth herein can include patterning using a first mask an isolation trench at a sidewall to sidewall isolation (SSI) region of a semiconductor structure having a substrate including fins and a main body section, filling the isolation trench at a SSI region with dielectric material, using a second mask to pattern an isolation trench at a single diffusion break (SDB) region, filling the isolation trench at the SDB region with dielectric material, and recessing dielectric material.

Abstract translation: 本文所述的方法可以包括使用第一掩模对具有包括鳍片和主体部分的衬底的半导体结构的侧壁至侧壁隔离（SSI）区域处的隔离沟槽进行图案化，在SSI区域处填充隔离沟槽， 电介质材料，使用第二掩模在单个扩散断裂（SDB）区域上图案化隔离沟槽，用介电材料填充SDB区域处的隔离沟槽，以及凹陷介电材料。

公开(公告)号：US20160104621A1

公开(公告)日：2016-04-14

申请号：US14512009

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L21/283 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/41775 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/088 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: In one aspect there is set forth herein a semiconductor device wherein a contact conductive layer and a gate conductive layer include a common conductive material. In one aspect a source/drain region contact conductive layer of an nFET, and a gate conductive layer of a gate of the nFET can be fabricated to include an n material. In one aspect a source/drain region contact conductive layer of a pFET, and a gate conductive layer of the pFET can be fabricated to include an p material.

Abstract translation: 在一个方面，这里阐述了半导体器件，其中接触导电层和栅极导电层包括公共导电材料。 在一个方面，nFET的源极/漏极区接触导电层和nFET的栅极的栅极导电层可被制造成包括n个材料。 在一个方面，可以制造pFET的源/漏区接触导电层和pFET的栅极导电层以包括p材料。

公开(公告)号：US20150380404A1

公开(公告)日：2015-12-31

申请号：US14315602

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/6681

Abstract: A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication.

Abstract translation: 提供起始非平面半导体结构，其具有半导体衬底，耦合到衬底的凸起的半导体结构以及围绕凸起结构的隔离材料层。 将隔离层凹入以露出约40nm至约70nm的凸起结构。 与常规的相比，暴露的凸起结构的增加的高度允许更高的栅极和较高的间隔物，这减少了在间隔物下的底切以及由制造中的隔离材料损失引起的短沟道效应。

公开(公告)号：US20200312718A1

公开(公告)日：2020-10-01

申请号：US16367733

申请日：2019-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US20200185266A1

公开(公告)日：2020-06-11

申请号：US16213189

申请日：2018-12-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Jessica M. DECHENE

IPC: H01L21/762 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.