公开(公告)号：US20160276345A1

公开(公告)日：2016-09-22

申请号：US15049391

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Bingwu LIU ,  Hui ZANG ,  Lun ZHAO

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US20160225762A1

公开(公告)日：2016-08-04

申请号：US14609564

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417 ,  H01L21/02 ,  H01L27/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3213

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/66545

Abstract: Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.

Abstract translation: 提供了形成在SDB上形成的部分或完全绝缘体结构的SDB和所得到的器件的方法。 实施例包括在衬底中形成具有第一宽度的SDB; 在所述SDB顶部的ILD中形成第一金属栅极，第二宽度大于所述第一宽度; 在第一金属栅极的相对侧上的衬底上的ILD中形成第二和第三金属栅极，第二和第三金属栅极与第一金属栅极横向分离; 在第二和第三栅极上形成光致抗蚀剂; 将第一金属栅极移到SDB上，形成空腔; 去除光致抗蚀剂; 并用绝缘体层填充空腔。

公开(公告)号：US20150129983A1

公开(公告)日：2015-05-14

申请号：US14079757

申请日：2013-11-14

Applicant: Globalfoundries Inc.

Inventor： Hong YU ,  Hyucksoo YANG ,  Bingwu LIU ,  Puneet KHANNA ,  Lun ZHAO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract translation: 鳍型晶体管制造方法和结构被提供具有延伸的嵌入应力元件。 所述方法包括例如：提供在衬底上延伸的翅片上延伸的栅极结构; 使用各向同性蚀刻和各向异性蚀刻在翅片内形成延伸空腔，其中延伸空腔部分地削弱了栅极结构，并且其中使用各向同性蚀刻和各向异性蚀刻将扩展腔加深到底切栅结构下方的翅片 ; 以及至少部分地在所述延伸空腔内形成嵌入的应力元件，包括在所述栅极结构下方。

公开(公告)号：US20210005605A1

公开(公告)日：2021-01-07

申请号：US16503982

申请日：2019-07-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wenjun LI ,  Brian J. GREENE ,  Tao CHU ,  Bingwu LIU

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

公开(公告)号：US20160322384A1

公开(公告)日：2016-11-03

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU ,  Xusheng WU

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。

公开(公告)号：US20160225848A1

公开(公告)日：2016-08-04

申请号：US14609653

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L21/3105

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/28017 ,  H01L21/28238 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/1079 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a SDB including a protective layer or bilayer and the resulting device are provided. Embodiments include forming a SDB of oxide in a Si substrate; forming a nitride layer over the Si substrate; forming a photoresist over the SDB and a portion of the nitride layer; removing the nitride layer on opposite sides of the photoresist down to the Si substrate, leaving a portion of the nitride layer only under the photoresist; forming a gate above the SBD and the portion of the nitride layer.

Abstract translation: 提供了形成包括保护层或双层的SDB的方法和所得到的器件。 实施例包括在Si衬底中形成氧化物的SDB; 在Si衬底上形成氮化物层; 在所述SDB和所述氮化物层的一部分上形成光致抗蚀剂; 将光致抗蚀剂的相对侧上的氮化物层去除到Si衬底，留下一部分氮化物层仅在光致抗蚀剂下面; 在SBD上方形成栅极和氮化物层的部分。

公开(公告)号：US20160365451A1

公开(公告)日：2016-12-15

申请号：US14735283

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Abstract translation: 提供了用于鳍式场效应晶体管（FinFet）器件的生长非成形外延的器件和方法。 一种方法包括例如：获得具有至少一个源，至少一个漏极和至少一个鳍片的晶片; 蚀刻以暴露所述至少一个翅片的至少一部分; 形成至少一个牺牲栅结构; 以及在所述至少一个翅片上形成外延生长的第一层。 一个装置包括例如：具有至少一个源的晶片，至少一个漏极和至少一个鳍片; 在所述至少一个翅片上的外延生长的第一层; 外延生长的至少一个第二层叠加第一层外延生长; 以及在所述至少一个源极上的第一接触区域和在所述至少一个漏极上的第二接触区域。

公开(公告)号：US20160225901A1

公开(公告)日：2016-08-04

申请号：US15091910

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/161 ,  H01L27/12 ,  H01L29/10 ,  H01L29/16 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US20160118386A1

公开(公告)日：2016-04-28

申请号：US14525763

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US20160118304A1

公开(公告)日：2016-04-28

申请号：US14524628

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L21/8238 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract translation: 提出了用于促进纳米线结构的制造的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括，例如：提供基底; 在所述衬底上方提供第一材料层和第二材料层，所述第一材料层与所述第二材料层交错; 去除第一材料层和第二材料层的部分，去除形成多个纳米线堆叠，包括第一材料纳米线和第二材料纳米线; 从至少一个纳米线堆叠去除所述第一材料纳米线; 以及从至少一个其它纳米线堆叠去除所述第二材料纳米线，其中所述至少一个纳米线堆叠和至少一个其它纳米线堆叠分别包括p型纳米线堆叠和n型纳米线堆叠 。