公开(公告)号：US11803009B2

公开(公告)日：2023-10-31

申请号：US17680421

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Steven M. Shank ,  Judson Holt

IPC: G02B6/122 ,  G02B6/136 ,  H01L21/84

CPC classification number: G02B6/122 ,  G02B6/136 ,  H01L21/84

Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.

公开(公告)号：US11749727B2

公开(公告)日：2023-09-05

申请号：US17546200

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu ,  Alexander Derrickson

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/401 ,  H01L29/66242 ,  H01L29/7371

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.

公开(公告)号：US20230137751A1

公开(公告)日：2023-05-04

申请号：US17872047

申请日：2022-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey

IPC: H01L29/735 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure comprises a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further comprises a modulator including a semiconductor layer in direct contact with the base layer. The base layer has a first conductivity type, and the semiconductor layer has a second conductivity type opposite to the first conductivity type.

公开(公告)号：US20230120538A1

公开(公告)日：2023-04-20

申请号：US17680434

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.

公开(公告)号：US20230084007A1

公开(公告)日：2023-03-16

申请号：US17574785

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson Holt

IPC: H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.

公开(公告)号：US11158633B1

公开(公告)日：2021-10-26

申请号：US16842075

申请日：2020-04-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Shesh Mani Pandey ,  Lixia Lei ,  Gregory Costrini

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78

Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

公开(公告)号：US11094827B2

公开(公告)日：2021-08-17

申请号：US16434136

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yanping Shen ,  Xiaoxiao Zhang ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.

公开(公告)号：US20210151451A1

公开(公告)日：2021-05-20

申请号：US16683439

申请日：2019-11-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh Mani Pandey

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

公开(公告)号：US10985244B2

公开(公告)日：2021-04-20

申请号：US16451797

申请日：2019-06-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shesh Mani Pandey ,  Chung Foong Tan ,  Baofu Zhu

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.