公开(公告)号：US20120319132A1

公开(公告)日：2012-12-20

申请号：US13162407

申请日：2011-06-16

申请人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

发明人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7806

摘要： An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.

摘要翻译： 集成结构包括多个分离栅沟槽MOSFET。 在碳化硅衬底组合物中形成多个沟槽，每个沟槽衬有钝化层，每个沟槽基本上填充有第一导电区域，第二导电区域和绝缘材料，其介电常数类似于介电常数 碳化硅衬底组合物。 第一导电区域通过绝缘材料与钝化层分离。 第一和第二导电区域形成每个沟槽MOSFET的栅极区域。 第一导电区域通过钝化层与第二导电区域分离。 在衬底组合物的上部形成的第一导电类型的掺杂体区域和形成在掺杂体区域内的第二导电类型的掺杂源区。

公开(公告)号：US20100276779A1

公开(公告)日：2010-11-04

申请号：US12433358

申请日：2009-04-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/34 ,  H01L21/265 ,  H01L21/76 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

公开(公告)号：US20160181391A1

公开(公告)日：2016-06-23

申请号：US14573187

申请日：2014-12-17

申请人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

发明人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/868

CPC分类号： H01L29/868 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7839 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/8725

摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体器件。 半导体器件包括在第一主表面上的第一导电类型的第一半导体层。 半导体器件还包括与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。 该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

公开(公告)号：US08710627B2

公开(公告)日：2014-04-29

申请号：US13171037

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L21/82222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/66

CPC分类号： H01L27/0262 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0814 ,  H01L27/082

摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

摘要翻译： 外延层支撑在基板的顶部。 第一和第二体区域形成在外延层中以预定的横向距离分开。 在外延层内形成触发源区和源极区。 第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。 第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。 第三源区域与第四触发区域横向相邻。 第四触发区域在第二和第三源区之间。 第四触发区域内的植入区域与第三源区域横向相邻。

公开(公告)号：US08476698B2

公开(公告)日：2013-07-02

申请号：US12709114

申请日：2010-02-19

申请人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

发明人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

IPC分类号： H01L29/72

CPC分类号： H01L29/7823 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/47 ,  H01L29/7811

摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

公开(公告)号：US08288839B2

公开(公告)日：2012-10-16

申请号：US12433358

申请日：2009-04-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/866

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，其中外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

公开(公告)号：US20110049564A1

公开(公告)日：2011-03-03

申请号：US12584151

申请日：2009-08-31

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66325 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

摘要翻译： 本发明公开了一种在半导体衬底中制造半导体功率器件的方法，包括有源电池区域和端接区域。 该方法包括以下步骤：a）在终端区域以及半导体衬底的顶表面上的活性单元区域中生长和构图场氧化物层b）在半导体衬底的顶表面上沉积并构图多晶硅层 在距离场氧化物层的间隙距离处; c）执行空白体掺杂剂注入以在所述半导体衬底中形成与所述间隙区基本对准的体掺杂区，随后将所述体掺杂区扩散到所述半导体衬底中的体区; d）植入包含在并且具有比身体区域更高的掺杂剂浓度的高浓度体 - 掺杂剂区域，以及e）将源掩模施加到具有与身体区域相反的导电性的源区域，其中源区域包含在身体区域中， 被高浓度体 - 掺杂区域包围。

公开(公告)号：US09620584B2

公开(公告)日：2017-04-11

申请号：US14454696

申请日：2014-08-07

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

公开(公告)号：US08933506B2

公开(公告)日：2015-01-13

申请号：US12931429

申请日：2011-01-31

申请人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

发明人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

IPC分类号： H01L29/66 ,  H01L29/739

CPC分类号： H01L29/7391

摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体器件。 半导体器件包括在第一主表面上的第一导电类型的第一半导体层。 半导体器件还包括在与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。 该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

公开(公告)号：US08338854B2

公开(公告)日：2012-12-25

申请号：US12384185

申请日：2009-03-31

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

IPC分类号： H01L29/866

CPC分类号： H01L29/866 ,  H01L27/0259 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/0657

摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.

摘要翻译： 一种设置在第一导电类型的半导体衬底上的瞬态电压抑制（TVS）器件。 TVS包括第二导电类型的掩埋掺杂区域，其被布置和包围在第一导电类型的外延层中，其中掩埋掺杂剂区域横向延伸并且具有与外延层的下面部分接合的延伸的底部接合区域，从而构成 用于TVS器件的齐纳二极管。 TVS器件还包括掩埋掺杂剂区域上方的区域，还包括第二导电类型的顶部掺杂剂层和第二导电类型的顶部接触区域，其与外延层和掩埋掺杂剂区域结合起来以形成多个 连接构成SCR作为转向二极管的PN结与用于抑制瞬态电压的齐纳二极管起作用的PN结。