公开(公告)号：US08754498B2

公开(公告)日：2014-06-17

申请号：US12606497

申请日：2009-10-27

申请人： Yue-Der Chih ,  Chrong Jung Lin

发明人： Yue-Der Chih ,  Chrong Jung Lin

IPC分类号： H01L29/86

CPC分类号： H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

摘要翻译： 制造反熔丝的方法包括提供具有位线扩散区域和电容器扩散区域的衬底。 栅极电介质层形成在衬底上，并且在栅极电介质层上形成字线。 在形成栅极电介质层的分离工艺步骤中，在电容器扩散区上形成氧化物层。 在上方形成选择线接触并与氧化物层接触以形成具有作为电容器的电容器电介质层的氧化物层的电容器。 选择线触点被配置为施加电压以导致氧化物层的永久性击穿来编程反熔丝。

公开(公告)号：US08687412B2

公开(公告)日：2014-04-01

申请号：US13438006

申请日：2012-04-03

申请人： Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

发明人： Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1673

摘要： A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

摘要翻译： 参考电路识别诸如位单元的磁阻存储元件的高或低电阻状态。 参考电路具有互补的高电阻状态RH和低电阻状态RL的磁隧道结（MTJ）元件，提供用于与存储元件进行比较的电压，电流或其它参数以识别电阻状态。 该参数表示由RH和RL跨过的中间电阻，例如平均或两倍平行的电阻。 参考MTJ元件从与存储元件相同的读取电流源偏置，但它们的磁性层在物理上或沿着偏置电流路径的顺序是相反的顺序。 参考MTJ元件被偏置以排除任何读取干扰风险。 存储器位单元沿着可比较的路径耦合到相同的偏置极性源，在其两种可能的逻辑状态之一中可以避免读取干扰风险。

公开(公告)号：US08674751B2

公开(公告)日：2014-03-18

申请号：US13447594

申请日：2012-04-16

申请人： Justin Shi ,  Yue-Der Chih

发明人： Justin Shi ,  Yue-Der Chih

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage.

摘要翻译： 在由低电压电力供电的集成电路器件中产生参考电压的方法包括：使用粗略参考发生器产生粗略的第一参考电压，将粗略的第一参考电压作为输入参考电压布置为升压调节器， 切换开关电路，所述升压调节器基于所述第一参考电压产生初始状态升压电源，以及使用罚款从所述升压电源电压产生第二更准确的参考电压的至少两个输出 分辨率参考发生器。 然后可以将第二参考信号环回到升压调节器，从而产生更准确的稳态升压电源电压。

公开(公告)号：US08325521B2

公开(公告)日：2012-12-04

申请号：US12900608

申请日：2010-10-08

申请人： Chia-Ta Hsieh ,  Yue-Der Chih

发明人： Chia-Ta Hsieh ,  Yue-Der Chih

IPC分类号： G11C16/26

CPC分类号： G11C16/08 ,  G11C16/26 ,  G11C16/3418

摘要： A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.

摘要翻译： 一种对包括多个闪存单元的存储器件执行读取操作的方法。 该方法包括将第一电压偏压施加到闪速存储器阵列中所选存储单元的控制栅极，并将第二电压偏压施加到所选存储单元的字线。 闪速存储器阵列中的未选择存储单元的控制栅极接地，并且第三电压偏压被施加到未选择单元的字线以关闭未选择的存储单元的字线通道。 选择的存储单元和未选择的存储单元被配置在存储器件中并被连接到不同的字线。 第一电压偏置和第二电压偏置具有相同的极性。 第三电压偏置和第二电压偏置具有相反的极性。

公开(公告)号：US08238178B2

公开(公告)日：2012-08-07

申请号：US12704676

申请日：2010-02-12

申请人： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

发明人： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC分类号： G11C7/00 ,  G11C11/34

CPC分类号： G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

摘要： A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

摘要翻译： 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三IO接口耦合的第三存储器阵列和与第四TO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

公开(公告)号：US20120163086A1

公开(公告)日：2012-06-28

申请号：US12979425

申请日：2010-12-28

申请人： Tien-Chung Yang ,  Chia-Fu Lee ,  Yue-Der Chih

发明人： Tien-Chung Yang ,  Chia-Fu Lee ,  Yue-Der Chih

IPC分类号： G11C16/08

CPC分类号： G11C16/06 ,  G11C16/30 ,  G11C2216/22

摘要： A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.

摘要翻译： 设备包括地址存储设备。 第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。 第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中的所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。 第二电路包括被配置为接收第二地址的第二闪存。 第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。

公开(公告)号：US20110199845A1

公开(公告)日：2011-08-18

申请号：US12704676

申请日：2010-02-12

申请人： Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

发明人： Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC分类号： G11C29/00

CPC分类号： G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

摘要： A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

摘要翻译： 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三输入/输出（IO）接口耦合的第三存储器阵列和与第四IO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

公开(公告)号：US07495960B2

公开(公告)日：2009-02-24

申请号：US11524128

申请日：2006-09-20

申请人： Yue-Der Chih ,  Shih-Wei Wang ,  Derek Lin

发明人： Yue-Der Chih ,  Shih-Wei Wang ,  Derek Lin

IPC分类号： G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/3418 ,  G11C16/3427

摘要： An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

摘要翻译： 闪存单元阵列包括包括多行的第一扇区，其中每行连接到控制栅极线，第一行包括第一扇区中的第一闪存单元，第一控制栅极线连接控制栅极线， 第一行中的闪存单元的栅极，第一扇区中的第二行，并且包括与第一闪存单元共享公共源极线和相同位线的第二闪存单元;连接第二控制栅极线的第二控制栅极线 第二行中存储单元的控制栅极，其中第一和第二控制栅极线彼此断开，第二扇区包括多行，其中每行连接到控制栅极线，正高 电压（HV）驱动器，连接到第一扇区中的第一控制栅极线和第二扇区中的控制栅极线。

公开(公告)号：US07495958B2

公开(公告)日：2009-02-24

申请号：US11593398

申请日：2006-11-06

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  Y10T29/49002

摘要： An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.

摘要翻译： 布置成多行和多列的闪存单元阵列包括包括多个单元的第一行。 每个单元包括多个闪存单元，连接第一行中所有闪存单元的擦除栅极的擦除栅极线，连接第一行中所有闪存单元的源节点的源极线，连接字的字线 第一行中的所有闪存单元的线路节点和仅在该单元中连接闪速存储器单元的控制栅极的本地控制栅极（CG）线，其中每个局部CG线路与本地CG线路中的剩余局部CG线路断开连接 第一排。 该阵列还包括位线，每个位线连接同一列中闪存单元的位线节点。

公开(公告)号：US20080061354A1

公开(公告)日：2008-03-13

申请号：US11531295

申请日：2006-09-13

申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。