公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US09123566B2

公开(公告)日：2015-09-01

申请号：US13935324

申请日：2013-07-03

Applicant: IMEC

Inventor： Jerome Mitard ,  Liesbeth Witters

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Abstract translation: 公开了互补金属氧化物半导体（CMOS）器件和制造这种CMOS器件的方法。 在一些实施例中，示例CMOS器件可以包括衬底和形成在衬底上的缓冲层，其中缓冲层包括Si1-xGex，其中x小于0.5。 示例CMOS器件还可以包括一个或多个pMOS沟道层元件，其中每个pMOS沟道层元件包括Si1-yGey，并且其中y大于x。 示例CMOS器件还可以包括一个或多个nMOS沟道层元件，其中每个nMOS沟道层元件包括Si1-zGez，并且其中z小于x。 在一些实施例中，示例CMOS器件可以是鳍状场效应晶体管（FinFET）CMOS器件，并且还可以包括包括pMOS沟道层元件的第一鳍结构和包括nMOS沟道层元件的第二鳍结构 s）。

公开(公告)号：US08828826B2

公开(公告)日：2014-09-09

申请号：US14015531

申请日：2013-08-30

Applicant: IMEC ,  Taiwan Semiconductor Manufacturing Company, Ltd. ,  GLOBALFOUNDRIES Inc.

Inventor： Liesbeth Witters ,  Rita Vos ,  David Brunco ,  Marcus Johannes Henricus Van Dal

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/165 ,  H01L21/285 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.

Abstract translation: 提供了一种用于制造晶体管器件的方法，所述晶体管器件包括基于锗的沟道层，所述方法包括在设置在衬底上的包含锗的沟道层上提供栅极结构，所述栅极结构设置在锗基源极区域和 在锗的相对侧的基于锗的漏极区域包括沟道层; 在锗基源和锗基漏极区上提供覆盖层，封盖层包含Si和Ge; 在覆盖层上沉积金属层; 进行温度步骤，从而将至少部分封盖层转变为不溶于适于溶解金属的预定蚀刻剂的金属锗硅化物; 通过预定的蚀刻剂从衬底中选择性地去除未消耗的金属; 并提供前金属介电层。