公开(公告)号：US10236183B2

公开(公告)日：2019-03-19

申请号：US15652786

申请日：2017-07-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert ,  Rita Rooyackers

IPC: H01L29/778 ,  H01L21/762 ,  H01L21/18 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L29/04 ,  H01L21/84 ,  H01L29/78 ,  H01L23/66

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

公开(公告)号：US20180025911A1

公开(公告)日：2018-01-25

申请号：US15652786

申请日：2017-07-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert ,  Rita Rooyackers

IPC: H01L21/18 ,  H01L23/00 ,  H01L21/02 ,  H01L25/00 ,  H01L23/535 ,  H01L21/768 ,  H01L29/04 ,  H01L25/065

CPC classification number: H01L21/187 ,  H01L21/02387 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/845 ,  H01L23/535 ,  H01L23/66 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/04 ,  H01L29/20 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7787 ,  H01L29/7851 ,  H01L2224/32501

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

公开(公告)号：US20160064535A1

公开(公告)日：2016-03-03

申请号：US14841566

申请日：2015-08-31

Applicant: IMEC VZW

Inventor： Anne S. Verhulst ,  Geoffrey Pourtois ,  Rita Rooyackers

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66977 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

Abstract translation: 提供隧道场效应晶体管（TFET）器件，其包括源极区域和沟道区域之间的至少一个异源区域。 所述至少一个杂交具有低介电常数和低于10nm的厚度。 此外，可以在至少一个异源区域和沟道区域之间加入口袋区域和另一杂交。

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US20170170313A1

公开(公告)日：2017-06-15

申请号：US15351504

申请日：2016-11-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Katia Devriendt ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  C30B29/40 ,  H01L21/02 ,  H01L29/66 ,  C30B25/04 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7827 ,  C30B25/04 ,  C30B29/06 ,  C30B29/08 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78642

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

公开(公告)号：US09608094B2

公开(公告)日：2017-03-28

申请号：US14841566

申请日：2015-08-31

Applicant: IMEC VZW

Inventor： Anne S. Verhulst ,  Geoffrey Pourtois ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/94 ,  H01L29/772 ,  H01L29/775 ,  H01L29/778 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

公开(公告)号：US09257539B2

公开(公告)日：2016-02-09

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

公开(公告)号：US20150179755A1

公开(公告)日：2015-06-25

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。