公开(公告)号：US20180108526A1

公开(公告)日：2018-04-19

申请号：US15787605

申请日：2017-10-18

Applicant: IMEC VZW

Inventor： Jerome Mitard

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02603 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to semiconductor devices comprising nanowires. In one aspect, a method of fabricating a semiconductor device includes providing a semiconductor substrate having one or more elongated structures thereon and forming a strained layer of semiconductor material on at least one surface of the elongated structures, and annealing the strained layer to form a semiconductor nanowire.

公开(公告)号：US09123566B2

公开(公告)日：2015-09-01

申请号：US13935324

申请日：2013-07-03

Applicant: IMEC

Inventor： Jerome Mitard ,  Liesbeth Witters

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Abstract translation: 公开了互补金属氧化物半导体（CMOS）器件和制造这种CMOS器件的方法。 在一些实施例中，示例CMOS器件可以包括衬底和形成在衬底上的缓冲层，其中缓冲层包括Si1-xGex，其中x小于0.5。 示例CMOS器件还可以包括一个或多个pMOS沟道层元件，其中每个pMOS沟道层元件包括Si1-yGey，并且其中y大于x。 示例CMOS器件还可以包括一个或多个nMOS沟道层元件，其中每个nMOS沟道层元件包括Si1-zGez，并且其中z小于x。 在一些实施例中，示例CMOS器件可以是鳍状场效应晶体管（FinFET）CMOS器件，并且还可以包括包括pMOS沟道层元件的第一鳍结构和包括nMOS沟道层元件的第二鳍结构 s）。

公开(公告)号：US09478544B2

公开(公告)日：2016-10-25

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括提供具有由介电材料结构限定的侧壁并邻接在硅衬底表面上的侧壁的沟槽，以及在表面上的沟槽中生长晶种层， 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US20140008730A1

公开(公告)日：2014-01-09

申请号：US13935324

申请日：2013-07-03

Applicant: IMEC

Inventor： Jerome Mitard ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Abstract translation: 公开了互补金属氧化物半导体（CMOS）器件和制造这种CMOS器件的方法。 在一些实施例中，示例CMOS器件可以包括衬底和形成在衬底上的缓冲层，其中缓冲层包括Si1-xGex，其中x小于0.5。 示例CMOS器件还可以包括一个或多个pMOS沟道层元件，其中每个pMOS沟道层元件包括Si1-yGey，并且其中y大于x。 示例CMOS器件还可以包括一个或多个nMOS沟道层元件，其中每个nMOS沟道层元件包括Si1-zGez，并且其中z小于x。 在一些实施例中，示例CMOS器件可以是鳍状场效应晶体管（FinFET）CMOS器件，并且还可以包括包括pMOS沟道层元件的第一鳍结构和包括nMOS沟道层元件的第二鳍结构 s）。

公开(公告)号：US09991261B2

公开(公告)日：2018-06-05

申请号：US15221396

申请日：2016-07-27

Applicant: IMEC VZW

Inventor： Jerome Mitard

IPC: H01L27/092 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/092 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. The n-type nanowire comprises a first material and the p-type nanowire comprises an inner part having two sides and an outer part at each side of the inner part in the longitudinal direction, wherein one or both of the two outer parts comprises a second material different from the first material. The n-type nanowire and the p-type nanowire each comprises a channel region electrically coupled to respective source and drain regions. The channel region of the p-type nanowire comprises the inner part. The device additionally includes a shared gate structure circumferentially surrounding the channel regions of the n-type and p-type nanowires.

公开(公告)号：US09502415B2

公开(公告)日：2016-11-22

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。

公开(公告)号：US20170040321A1

公开(公告)日：2017-02-09

申请号：US15221396

申请日：2016-07-27

Applicant: IMEC VZW

Inventor： Jerome Mitard

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/092 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. The n-type nanowire comprises a first material and the p-type nanowire comprises an inner part having two sides and an outer part at each side of the inner part in the longitudinal direction, wherein one or both of the two outer parts comprises a second material different from the first material. The n-type nanowire and the p-type nanowire each comprises a channel region electrically coupled to respective source and drain regions. The channel region of the p-type nanowire comprises the inner part. The device additionally includes a shared gate structure circumferentially surrounding the channel regions of the n-type and p-type nanowires.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及一种全封闭栅极（GAA）半导体器件及其制造方法。 一方面，半导体器件具有在衬底上形成的纳米线的垂直堆叠，其中纳米线的垂直堆叠包括n个纳米线和p型纳米线，每个n型纳米线和p型纳米线在平行于衬底的主表面的纵向方向上延伸 。 n型纳米线包括第一材料，p型纳米线包括具有两侧的内部部分和在纵向方向上的内部部分的每一侧的外部部分，其中两个外部部件中的一个或两个包括第二部分 材料与第一种材料不同。 n型纳米线和p型纳米线各自包括电耦合到相应的源极和漏极区域的沟道区域。 p型纳米线的沟道区域包括内部部分。 该器件还包括周向围绕n型和p型纳米线的沟道区的共享栅极结构。

公开(公告)号：US20160027780A1

公开(公告)日：2016-01-28

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括：提供具有由介电材料结构限定的侧壁并邻接在硅衬底的表面上并具有在表面上的沟槽中的种子层的沟槽，其中 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US20160027779A1

公开(公告)日：2016-01-28

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。

公开(公告)号：US20130181301A1

公开(公告)日：2013-07-18

申请号：US13725587

申请日：2012-12-21

Applicant: IMEC ,  Katholieke Universiteit Leuven

Inventor： Liesbeth Witters ,  Jerome Mitard ,  Geert Hellings

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess.

Abstract translation: 公开了制造半导体器件的方法。 一方面，该方法包括：在衬底层上形成虚拟栅极; 形成与所述虚拟栅极的侧壁相邻并且在所述衬底层上方的第一栅极绝缘间隔物，所述第一间隔物具有两个侧壁和两个表面轮廓，其中所述侧壁与所述衬底层相遇; 使用所述表面轮廓形成源极和漏极区域; 形成与所述第一间隔物的侧壁相邻并且在所述源极和漏极区域上的第二栅极绝缘间隔物; 去除所述伪栅极和所述第一间隔物，从而形成第一凹部; 在所述第一凹部中沿所述第二间隔物的侧壁和所述基底层上沉积介电层，由此形成第二凹槽; 以及在所述第二凹部中沉积栅电极。