公开(公告)号：US20220068740A1

公开(公告)日：2022-03-03

申请号：US17088621

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/14 ,  H01R12/71

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may include a semiconductor package including an interposer with a molded portion, and one or more of semiconductor devices. The one or more semiconductor devices may have at least a first device coupled to the molded portion. The device may include a first connector coupled to the molded portion, and a second connector coupled to the printed circuit board, the first connector and the second connector configured to be connected with a cable for signal connection between the first device and the printed circuit board.

公开(公告)号：US20210410273A1

公开(公告)日：2021-12-30

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM ,  Chin Lee KUAN ,  Tin Poay CHUAH

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US20210384135A1

公开(公告)日：2021-12-09

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Sameer SHEKHAR ,  Amit JAIN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

公开(公告)号：US20210335718A1

公开(公告)日：2021-10-28

申请号：US17368837

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.

公开(公告)号：US20210335698A1

公开(公告)日：2021-10-28

申请号：US17367684

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Chia Chuan WU ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

公开(公告)号：US20180366407A1

公开(公告)日：2018-12-20

申请号：US15982912

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Ping Ping OOI ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Mooi Ling CHANG ,  Wen Wei LUM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/367

Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage. One or more conductive traces may connect the conductive features in the interior with conductive features in the periphery.

公开(公告)号：US20240429131A1

公开(公告)日：2024-12-26

申请号：US18824468

申请日：2024-09-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L25/16

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20240234283A9

公开(公告)日：2024-07-11

申请号：US17968830

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

公开(公告)号：US20240145450A1

公开(公告)日：2024-05-02

申请号：US18050527

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Amit JAIN ,  Sameer SHEKHAR

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.

公开(公告)号：US20240006376A1

公开(公告)日：2024-01-04

申请号：US17857062

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06582 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06513

Abstract: A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.