公开(公告)号：US20220181445A1

公开(公告)日：2022-06-09

申请号：US17679875

申请日：2022-02-24

Applicant: Intel Corporation ,  Technische Universiteit Delft

Inventor： Kanwaljit Singh ,  James S. Clarke ,  Menno Veldhorst ,  Lieven Mark Koenraad Vandersypen

IPC: H01L29/15 ,  G06N10/00 ,  H01L23/473 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/775

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

公开(公告)号：US20220158069A1

公开(公告)日：2022-05-19

申请号：US17592724

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC: H01L39/22 ,  G06N10/00 ,  H01L39/02 ,  H01L39/24

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

公开(公告)号：US11288586B2

公开(公告)日：2022-03-29

申请号：US16320153

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L29/423 ,  G06N10/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

公开(公告)号：US20210376102A1

公开(公告)日：2021-12-02

申请号：US17401692

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/06

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

公开(公告)号：US20210343845A1

公开(公告)日：2021-11-04

申请号：US17368427

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L29/40 ,  H01L29/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/76 ,  H01L23/532 ,  B82Y40/00 ,  B82Y10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

公开(公告)号：US20210328019A1

公开(公告)日：2021-10-21

申请号：US17364985

申请日：2021-07-01

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US11114530B2

公开(公告)日：2021-09-07

申请号：US16648442

申请日：2017-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US11075293B2

公开(公告)日：2021-07-27

申请号：US16328670

申请日：2016-09-24

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/775 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L25/00 ,  H01L25/16 ,  B82Y10/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L25/11 ,  H01L21/56 ,  H01L29/165

Abstract: Disclosed herein are qubit-detector die assemblies, as well as related computing devices and methods. In some embodiments, a die assembly may include: a first die having a first face and an opposing second face, wherein a plurality of active qubit devices are disposed at the first face of the first die; and a second die, mechanically coupled to the first die, having a first face and an opposing second face, wherein a plurality of quantum state detector devices are disposed at the first face of the second die; wherein the first faces of the first and second dies face each other.

公开(公告)号：US11063138B2

公开(公告)日：2021-07-13

申请号：US16616350

申请日：2017-06-24

Applicant: Intel Corporation ,  Technische Universiteit Delft

Inventor： Kanwaljit Singh ,  James S. Clarke ,  Menno Veldhorst ,  Lieven Mark Koenraad Vandersypen

IPC: H01L29/66 ,  G06N10/00 ,  H01L27/088 ,  H01L29/43 ,  H01L29/49 ,  H01L29/12 ,  H01L27/105 ,  H01L29/82

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

公开(公告)号：US10803396B2

公开(公告)日：2020-10-13

申请号：US16011812

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  Roman Caudillo ,  Ravi Pillarisetty ,  Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: G06N10/00 ,  H01L27/18 ,  H03K19/195 ,  B82Y10/00 ,  H03K17/92 ,  G11C11/44 ,  H01L45/00 ,  H01L39/22 ,  H01L39/24 ,  H01L29/66

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.