公开(公告)号：US20180236440A1

公开(公告)日：2018-08-23

申请号：US15772839

申请日：2015-12-04

Applicant: Jeffery D. BIELEFELD ,  James M. BLACKWELL ,  David J. MICHALAK ,  Jessica M. TORRES ,  Marie KRYSAK ,  Intel Corporation

Inventor： James M. BLACKWELL ,  David J. Michalak ,  Jessica M. Torres ,  Marie KRYSAK ,  Jeffery D. Bielefeld

IPC: B01J37/08 ,  B01J31/02 ,  B01J21/02 ,  C08L83/16 ,  C08J3/24 ,  H01B3/46

CPC classification number: B01J37/08 ,  B01J21/02 ,  B01J31/0284 ,  C08J3/245 ,  C08L83/16 ,  H01B3/22 ,  H01B3/46

Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner. Protected catalysts disclosed herein allow careful control of precursor cross-linking, resulting in higher quality dielectric materials that may be formed by coating techniques.

公开(公告)号：US20200098629A1

公开(公告)日：2020-03-26

申请号：US16465526

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC: H01L21/768

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US10388848B2

公开(公告)日：2019-08-20

申请号：US15924410

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Lester Lampert ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L39/02 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  H03K17/92 ,  G06N10/00

Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.

公开(公告)号：US20210036110A1

公开(公告)日：2021-02-04

申请号：US16648442

申请日：2017-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US10763347B2

公开(公告)日：2020-09-01

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  G06N10/00 ,  H01L21/02 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/76 ,  H01L29/423 ,  H01L29/40 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US11869894B2

公开(公告)日：2024-01-09

申请号：US17864264

申请日：2022-07-13

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/28568 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H10B61/22 ,  H10B63/30

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US11152254B2

公开(公告)日：2021-10-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Sudipto Naskar ,  Stephanie A. Bojarski ,  Kevin Lin ,  Marie Krysak ,  Tristan A. Tronic ,  Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Jessica M. Torres

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US11024538B2

公开(公告)日：2021-06-01

申请号：US16465526

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC: H01L21/768

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US20190334020A1

公开(公告)日：2019-10-31

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US20190044045A1

公开(公告)日：2019-02-07

申请号：US15924410

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Lester Lampert ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L39/02 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  H03K17/92 ,  G06N99/00

CPC classification number: H01L39/025 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/127 ,  H01L29/423 ,  H01L29/66439 ,  H01L29/66977 ,  H01L29/66984 ,  H01L29/7613 ,  H01L39/045 ,  H01L39/223 ,  H01L39/249 ,  H01L39/2493 ,  H03K17/92

Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.