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    MULTI-PORTED REGISTER FILE WITH CFETS
    46.
    发明公开
    MULTI-PORTED REGISTER FILE WITH CFETS 审中-公开

    公开(公告)号：US20240053987A1

    公开(公告)日：2024-02-15

    申请号：US17887154

    申请日：2022-08-12

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

    IPC: G06F9/30

    CPC classification number: G06F9/30141 ,  G06F9/3012

    Abstract: An apparatus, system, and method for register file circuits are provided. A register file circuit can include a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, a second PMOS transistor including a source coupled to an output of the first inverter, and a second WBL (WBLB) coupled to a drain of the second PMOS transistor. 1R1W register file and 2R1W register file designs are provided.

    Multi-bit pulsed latch including serial scan chain
    47.
    发明授权
    Multi-bit pulsed latch including serial scan chain 有权

    公开(公告)号：US10410699B1

    公开(公告)日：2019-09-10

    申请号：US16024441

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Anupama A. Thaploo ,  Bhushan Borole ,  Muhammad M. Khellah ,  Pascal A. Meinerzhagen

    IPC: G11C7/22 ,  G01R31/3185

    Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT
    48.
    发明申请
    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20190198093A1

    公开(公告)日：2019-06-27

    申请号：US16226385

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/419 ,  G11C11/412

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

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