公开(公告)号：US10176111B2

公开(公告)日：2019-01-08

申请号：US15212492

申请日：2016-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Lisa Cranton Heller ,  Christian Jacobi ,  Damian L. Osisek ,  Anthony Saporito

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/121 ,  G06F12/1009

Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes an invalidation facility based on the setting of the indicators.

公开(公告)号：US20180365172A1

公开(公告)日：2018-12-20

申请号：US15844164

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Johannes C. Reichart ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/1045 ,  G06F12/1009 ,  G06F12/0817 ,  G06F12/0808 ,  G06F12/0811

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：US20180365164A1

公开(公告)日：2018-12-20

申请号：US15844239

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Martin Recktenwald ,  Johannes C. Reichart

IPC: G06F9/455

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：US20180365151A1

公开(公告)日：2018-12-20

申请号：US15833497

申请日：2017-12-06

Applicant: International Business Machines Corporation

Inventor： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/0817 ,  G06F12/0842 ,  G06F12/0831

CPC classification number: G06F12/0828 ,  G06F12/0822 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1024

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：US20180341480A1

公开(公告)日：2018-11-29

申请号：US15602618

申请日：2017-05-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jane H. Bartik ,  Christian Jacobi ,  David Lee ,  Jang-Soo Lee ,  Anthony Saporito ,  Christian Zoellin

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/30101 ,  G06F9/3867 ,  G06F11/36 ,  G06F11/3636

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

公开(公告)号：US20180225119A1

公开(公告)日：2018-08-09

申请号：US15428441

申请日：2017-02-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory W. Alexander ,  Stephen Duffy ,  David S. Hutton ,  Christian Jacobi ,  Anthony Saporito ,  Somin Song

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments include load-balancing a plurality of simultaneous threads of a processor. An example method includes computing a minimum group count for a thread from the plurality of threads. The minimum group count indicates a minimum number of groups of instructions to be assigned to the thread. The method further includes computing a maximum allowed group count for the thread. The maximum allowed group count indicates a maximum number of groups of instructions to be assigned to the thread. The method further includes issuing one or more groups of instructions for execution by the thread based on the minimum group count and the maximum allowed group count for the thread.

公开(公告)号：US10025589B2

公开(公告)日：2018-07-17

申请号：US15228067

申请日：2016-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3005 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30152 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

公开(公告)号：US20180107488A1

公开(公告)日：2018-04-19

申请号：US15836133

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/46 ,  G06F9/30

Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.

公开(公告)号：US09946588B2

公开(公告)日：2018-04-17

申请号：US14573388

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Gregory W. Alexander ,  Khary J. Alexander ,  Ilya Granovsky ,  Christian Jacobi ,  Gregory Miaskovsky ,  James R. Mitchell

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/30 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F11/073 ,  G06F1/3275 ,  G06F9/30 ,  G06F9/3826 ,  G06F9/3834 ,  G06F11/1666 ,  G06F11/3037 ,  Y02D10/13 ,  Y02D10/14

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

公开(公告)号：US09940264B2

公开(公告)日：2018-04-10

申请号：US14511408

申请日：2014-10-10

Applicant: International Business Machines Corporation

Inventor： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Martin Recktenwald

IPC: G06F12/12 ,  G06F12/08 ,  G06F9/38 ,  G06F9/52 ,  G06F12/128 ,  G06F12/0875 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/128 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/62

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.