公开(公告)号：US09159671B2

公开(公告)日：2015-10-13

申请号：US14083929

申请日：2013-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L21/4763 ,  H01L23/498 ,  H01L21/445 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract translation: 提供了在集成电路中制造铜线的方法。 制造半导体结构的方法包括在掩模中形成线开口。 该方法还包括在导线开口中电镀导电材料。 该方法还包括在导电材料上形成盖层。 该方法还包括去除掩模。 该方法还包括在导电材料的侧面上形成间隔物。 该方法还包括在盖层和侧壁间隔物的表面上形成电介质膜。

公开(公告)号：US20150262911A1

公开(公告)日：2015-09-17

申请号：US14211479

申请日：2014-03-14

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Charles W. Griffin ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L23/481 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372

Abstract: A through silicon via (TSV), method and 3D integrated circuit are disclosed. The TSV extends through a substrate to a back side of the substrate and includes a body including a first metal for coupling to an interconnect on a front side of the substrate. A dielectric collar insulates the body from the substrate. The TSV also includes an end cap coupled to the body on the back side of the substrate, the end cap including a second metal that is different than the first metal. The end cap acts as a grinding stop indicator during back side grinding for 3D integration processing, preventing damage to the dielectric collar and first metal (e.g., copper) contamination of the substrate.

Abstract translation: 公开了一种硅通孔（TSV），方法和3D集成电路。 TSV通过衬底延伸到衬底的背面，并且包括主体，该主体包括用于耦合到衬底的前侧上的互连的第一金属。 电介质套管使主体与衬底绝缘。 TSV还包括在基板背面连接到主体的端帽，端盖包括与第一金属不同的第二金属。 在用于3D一体化处理的后侧研磨期间，端盖用作研磨停止指示器，防止损坏介质套环和衬底的第一金属（例如铜）污染。

公开(公告)号：US20150221567A1

公开(公告)日：2015-08-06

申请号：US14689463

申请日：2015-04-17

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Roger A. Dufresne

IPC: H01L21/66 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.

Abstract translation: Kerf区域位于晶片上的集成电路芯片之间。 通过链条测试结构位于切口区域或测试芯片中。 通孔链测试结构包括在晶片的第一区域中的第一导体。 首先通过链条在各个点处连接到第一导体。 第一通孔链中的每一个包括从第一导体开始并在晶片的第二区域的绝缘区域结束的开放式电路。 通孔链测试结构包括第二区域中的第二导体。 第二通道链在各个点处连接到第二导体。 每个第二通孔链包括从第二导体开始并且终止于第一区域的绝缘区域的开放式电路。

公开(公告)号：US09093503B1

公开(公告)日：2015-07-28

申请号：US14146788

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin S. Petrarca ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2224/13

Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract translation: 公开了一种具有双镶嵌绝缘线和绝缘的穿通基板通孔（TSV）结构的半导体芯片以及形成芯片的方法。 所述方法包括双镶嵌技术，其中沟槽和通孔开口形成在衬底上方的电介质层中，使得沟槽位于第一通孔上方，并且通孔开口定位成与第一通孔相邻并且从沟槽垂直延伸并进入 基质。 电介质间隔物形成在沟槽和通孔开口的侧壁上。 沉积金属层以在沟槽中形成绝缘电线，并在通孔开口中形成绝缘的TSV。 因此，绝缘线将绝缘TSV与第一通孔电连接，从而将其连接到下面的片上器件或下部金属级线。 随后，将衬底变薄以暴露衬底底部的绝缘TSV。