公开(公告)号：US10177000B2

公开(公告)日：2019-01-08

申请号：US15425005

申请日：2017-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Thomas J. Hartswick ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L21/78 ,  H01L21/288 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/485 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/285 ,  H01L23/58 ,  H01L23/528 ,  C25D7/12 ,  C25D3/38 ,  C25D5/10

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US09230914B2

公开(公告)日：2016-01-05

申请号：US14526741

申请日：2014-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L27/08 ,  H01L29/00 ,  H01L21/76 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20150140809A1

公开(公告)日：2015-05-21

申请号：US14600273

申请日：2015-01-20

Applicant: International Business Machines Corporation

Inventor： David A. DeMuynck ,  Zhong-Xiang He ,  Daniel R. Miga ,  Matthew D. Moon ,  Daniel S. Vanslette ,  Eric J. White

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，更具体地，涉及高性能电感器。 IC包括设置在基板上的电介质层内的至少一个沟槽。 沟槽被保形地涂覆有衬里和种子层，并且包括内部的互连。 互连包括在互连的侧壁上的硬掩模。

公开(公告)号：US20140239448A1

公开(公告)日：2014-08-28

申请号：US13778321

申请日：2013-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  Zhong-Xiang He ,  Theodore J. Letavic ,  Yves T. Ngu

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

Abstract translation: 公开了一种叉指电容器和交叉指向的垂直原始电容器，每个电容器相对于特定参数具有相对较低（例如，零）的电容系数。 例如，电容器可以具有零线性电容温度系数（Tcc），以将电容变化限制为温度或零净二次电压电容系数（Vcc2），以将电容变化限制为电压的函数。 在任何情况下，由于所使用的介电材料的类型及其各自的厚度，每个电容器可以结合至少两个不同的平板电介质，其具有与特定参数相反的极性电容系数。 结果，不同的电介质板将对彼此抵消的电容器的电容产生相反的影响，使得电容器相对于特定参数具有零净电容系数。

公开(公告)号：US08815733B2

公开(公告)日：2014-08-26

申请号：US14076707

申请日：2013-11-11

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

IPC: H01L21/4763

CPC classification number: H01L21/32139 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.

公开(公告)号：US20140097434A1

公开(公告)日：2014-04-10

申请号：US13644918

申请日：2012-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L29/775 ,  G06F17/50 ,  H01L21/336

CPC classification number: H01L29/93 ,  H01L27/0688 ,  H01L27/0808

Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Abstract translation: 变容二极管的器件结构，设计结构和制造方法。 器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。 半导体本体由非晶态或多晶态的含硅半导体材料构成。 器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

公开(公告)号：US20130171817A1

公开(公告)日：2013-07-04

申请号：US13778263

申请日：2013-02-27

Applicant: International Business Machines Corporation

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao-Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

Abstract translation: 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。

公开(公告)号：US09613853B2

公开(公告)日：2017-04-04

申请号：US14883162

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L21/70 ,  H01L23/12 ,  H01L29/40 ,  H01L29/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/288

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US09437539B2

公开(公告)日：2016-09-06

申请号：US14830816

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09231046B2

公开(公告)日：2016-01-05

申请号：US13840132

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/60 ,  H01L2224/13009 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/19041

Abstract: A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad.

Abstract translation: 公开了一种使用阻挡层冶金和制造方法的金属绝缘体金属（MIM）电容器。 该方法包括使用单一掩蔽工艺形成金属 - 绝缘体 - 金属（MIM）电容器的底板和接合焊盘。 该方法还包括在底板上形成MIM电介质。 该方法还包括在MIM电介质上形成MIM电容器的顶板。 该方法还包括在焊盘上形成焊接连接​​。