ASYMMETRIC DIE BONDING
    43.
    发明申请

    公开(公告)号:US20220093556A1

    公开(公告)日:2022-03-24

    申请号:US17030360

    申请日:2020-09-23

    Abstract: An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.

    Connected plane stiffener within integrated circuit chip carrier

    公开(公告)号:US10770385B2

    公开(公告)日:2020-09-08

    申请号:US16046653

    申请日:2018-07-26

    Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

    Connected Plane Stiffener Within Integrated Circuit Chip Carrier

    公开(公告)号:US20200035593A1

    公开(公告)日:2020-01-30

    申请号:US16046653

    申请日:2018-07-26

    Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

Patent Agency Ranking