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公开(公告)号：US20170097389A1
公开(公告)日：2017-04-06
申请号：US15138737
申请日：2016-04-26
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
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公开(公告)号：US20160223606A1
公开(公告)日：2016-08-04
申请号：US15093190
申请日：2016-04-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Raphael P. Robertazzi , Peilin Song , Franco Stellari
CPC classification number: G01R31/2642 , G01R31/2607 , G01R31/2621 , G01R31/275 , G01R31/2855 , G01R31/3004 , G01R31/311
Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.
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公开(公告)号：US09184751B2
公开(公告)日：2015-11-10
申请号：US14028880
申请日：2013-09-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dirk Pfeiffer , Jean-Olivier Plouchart , Peilin Song
IPC: H03K19/003 , H04L9/20
CPC classification number: H03K19/003
Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.
Abstract translation: 公开了使用物理不可克隆功能（PUF）的芯片认证相关的方法，系统和设备。 根据一种这样的方法，将测试电压施加到包括串联布置的PUF元件的第一子集和串联布置的PUF元件的第二子集的PUF系统，其中PUF元件的第一子集被布置在 相对于PUF元件的第二子集平行。 此外，测量PUF系统以获得PUF元素的第一子集和PUF元素的第二子集之间的状态的至少一个差异。 此外，该方法包括输出基于一个或多个状态差分的电路的认证序列。
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公开(公告)号：US20150247892A1
公开(公告)日：2015-09-03
申请号：US14194156
申请日：2014-02-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Raphael P. Robertazzi , Peilin Song , Franco Stellari
CPC classification number: G01R31/2642 , G01R31/2607 , G01R31/2621 , G01R31/275 , G01R31/2855 , G01R31/3004 , G01R31/311
Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.
Abstract translation: 一种用于表征集成电路的方法，该集成电路包括使集成电路的电源电压随着集成电路中的每个晶体管的时间而变化，并且在电源电压斜坡期间测量集成电路的电源电流 。 电源电流中测量的峰值是识别每个晶体管处于导通状态的操作状态的电流脉冲。 将电源电流中的峰值与用于具有与集成电路相同功能的参考电路的电源电流的参考峰值进行比较，以确定集成电路的适合度。
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公开(公告)号：US11587890B2
公开(公告)日：2023-02-21
申请号：US16933549
申请日：2020-07-20
Applicant: International Business Machines Corporation
Inventor： Jean-Olivier Plouchart , Dirk Pfeiffer , Arvind Kumar , Takashi Ando , Peilin Song
Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.
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Patent Agency Ranking
公开(公告)号：US11508438B1
公开(公告)日：2022-11-22
申请号：US17072810
申请日：2020-10-16
Applicant: International Business Machines Corporation
Inventor： Franco Stellari , Takashi Ando , Cyril Cabral, Jr. , Eduard Albert Cartier , Martin Michael Frank , Peilin Song , Dirk Pfeiffer
Abstract: Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.
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公开(公告)号：US11106764B2
公开(公告)日：2021-08-31
申请号：US16684064
申请日：2019-11-14
Applicant: International Business Machines Corporation
Inventor： Andrea Bahgat Shehata , Peilin Song , Franco Stellari
IPC: G06F21/14 , G06F30/398 , G06F30/00 , G06F30/30
Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.
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公开(公告)号：US20210063482A1
公开(公告)日：2021-03-04
申请号：US16559597
申请日：2019-09-03
Applicant: International Business Machines Corporation
Inventor： Franco Stellari , Peilin Song
IPC: G01R31/311
Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT.
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公开(公告)号：US20210063481A1
公开(公告)日：2021-03-04
申请号：US16559589
申请日：2019-09-03
Applicant: International Business Machines Corporation
Inventor： Franco Stellari , Peilin Song
IPC: G01R31/311
Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to update the time-dependent map of the emissions based on combinations of the emissions of light at certain locations.
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公开(公告)号：US20200150181A1
公开(公告)日：2020-05-14
申请号：US16189295
申请日：2018-11-13
Applicant: International Business Machines Corporation
Inventor： Emily A. Ray , Emmanuel Yashchin , Peilin Song , Kevin G. Stawiasz , Barry Linder , Alan Weger , Keith A. Jenkins , Raphael P. Robertazzi , Franco Stellari , James Stathis
IPC: G01R31/3193 , G01R31/319
Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.
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