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公开(公告)号:US10896993B2
公开(公告)日:2021-01-19
申请号:US16381511
申请日:2019-04-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Jianshi Tang , Ning Li , Qing Cao
IPC: H01L31/18 , H04B10/11 , H01L33/58 , H01L31/0232 , H01L33/00
Abstract: A method and an apparatus are provided. The apparatus includes a three-dimensional semiconductor structure having a spherical array of fixed-position optoelectronic devices arranged over a relaxed elastomer by a controlled unbuckling process that orients the fixed-position optoelectronic devices to face in different directions in the spherical array to communicate in the different directions without motion of the apparatus and the fixed-position optoelectronic devices of the apparatus.
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公开(公告)号:US10665414B2
公开(公告)日:2020-05-26
申请号:US15801881
申请日:2017-11-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.
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公开(公告)号:US20200090896A1
公开(公告)日:2020-03-19
申请号:US16686833
申请日:2019-11-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.
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公开(公告)号:US10576268B2
公开(公告)日:2020-03-03
申请号:US15466171
申请日:2017-03-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Hariklia Deligianni , Fei Liu
IPC: A61N1/05 , H01L21/683 , H01L21/306 , H01L21/762 , H01L23/14 , A61B5/00 , A61N1/36 , A61B5/04
Abstract: Aspects include high resolution brain-electronic interfaces and related methods. Aspects include forming a semiconductor circuit on a substrate, depositing a tensile stress layer on the circuit, and separating the semiconductor circuit from a portion of the silicon substrate. Aspects also include removing the tensile stress layer from the semiconductor circuit and transferring the semiconductor circuit to a biocompatible film.
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公开(公告)号:US10468593B1
公开(公告)日:2019-11-05
申请号:US15950754
申请日:2018-04-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Jianshi Tang , Ning Li
IPC: H01L21/8238 , H01L45/00
Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
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公开(公告)号:US20190326229A1
公开(公告)日:2019-10-24
申请号:US16460323
申请日:2019-07-02
Applicant: International Business Machines Corporation
Inventor: Kangguo Cheng , Qing Cao , Fei Liu , Zhengwen Li
IPC: H01L23/00 , G01L1/16 , H01L41/311 , H01L27/20 , H01L41/25
Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.
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公开(公告)号:US20190319184A1
公开(公告)日:2019-10-17
申请号:US15950754
申请日:2018-04-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Jianshi Tang , Ning Li
IPC: H01L45/00
Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
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公开(公告)号:US10373908B2
公开(公告)日:2019-08-06
申请号:US15850564
申请日:2017-12-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC: H01L29/00 , H01L23/525 , H01L23/528 , H01L23/532 , H01L23/373 , H01L23/367 , H01L29/06 , H01L21/02 , H01L21/3205 , H01L21/8234 , H01L23/522
Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.
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公开(公告)号:US10319927B2
公开(公告)日:2019-06-11
申请号:US14951847
申请日:2015-11-25
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Shu-Jen Han , Jianshi Tang
Abstract: A method of forming an end-bonded contact on a semiconductor is disclosed herein. The method can include forming a dielectric layer on a substrate and depositing a carbon nanotube layer onto the dielectric layer. Additionally, the method can include depositing a resist mask onto the carbon nanotube layer and patterning the resist mask to form a contact mold such that a portion of the carbon nanotube layer is exposed. In some aspects, the method can include depositing a contact metal such that the contact metal contacts the exposed carbon nanotube layer and thermally annealing the device such that the carbon nanotube layer dissolves into the contact metal such that a single contact surface is formed between the contact and the carbon nanotube layer.
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公开(公告)号:US10319926B2
公开(公告)日:2019-06-11
申请号:US14933339
申请日:2015-11-05
Applicant: International Business Machines Corporation
Inventor: Qing Cao , Shu-Jen Han , Jianshi Tang
Abstract: A method of forming an end-bonded contact on a semiconductor is disclosed herein. The method can include forming a dielectric layer on a substrate and depositing a carbon nanotube layer onto the dielectric layer. Additionally, the method can include depositing a resist mask onto the carbon nanotube layer and patterning the resist mask to form a contact mold such that a portion of the carbon nanotube layer is exposed. In some aspects, the method can include depositing a contact metal such that the contact metal contacts the exposed carbon nanotube layer and thermally annealing the device such that the carbon nanotube layer dissolves into the contact metal such that a single contact surface is formed between the contact and the carbon nanotube layer.
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