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公开(公告)号：US10886467B2
公开(公告)日：2021-01-05
申请号：US16401693
申请日：2019-05-02
发明人： Hiroyuki Miyazoe , Qing Cao , Takashi Ando , John Rozen
摘要： A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.
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公开(公告)号：US20200350499A1
公开(公告)日：2020-11-05
申请号：US16401693
申请日：2019-05-02
发明人： Hiroyuki Miyazoe , Qing Cao , Takashi Ando , John Rozen
IPC分类号： H01L45/00
摘要： A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.
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公开(公告)号：US10777741B2
公开(公告)日：2020-09-15
申请号：US16666471
申请日：2019-10-29
发明人： Qing Cao , Jianshi Tang , Ning Li
IPC分类号： H01L21/8238 , H01L45/00
摘要： A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
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公开(公告)号：US20200136034A1
公开(公告)日：2020-04-30
申请号：US16666471
申请日：2019-10-29
发明人： Qing Cao , Jianshi Tang , Ning Li
IPC分类号： H01L45/00
摘要： A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
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公开(公告)号：US10586864B2
公开(公告)日：2020-03-10
申请号：US16055128
申请日：2018-08-05
发明人： Jianshi Tang , Qing Cao
IPC分类号： H01L29/78 , H01L29/66 , H01L21/285 , H01L21/8234 , H01L21/308 , H01L29/417
摘要： A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.
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公开(公告)号：US10573482B2
公开(公告)日：2020-02-25
申请号：US15418807
申请日：2017-01-30
发明人： Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
摘要： A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.
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公开(公告)号：US20200044082A1
公开(公告)日：2020-02-06
申请号：US16055128
申请日：2018-08-05
发明人： Jianshi Tang , Qing Cao
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8234 , H01L21/308 , H01L21/285
摘要： A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.
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公开(公告)号：US10431557B2
公开(公告)日：2019-10-01
申请号：US15911608
申请日：2018-03-05
发明人： Kangguo Cheng , Qing Cao , Fei Liu , Zhengwen Li
IPC分类号： H01L23/00 , H01L27/20 , H01L41/25 , H01L41/311 , G01L1/16
摘要： The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.
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公开(公告)号：US10355118B2
公开(公告)日：2019-07-16
申请号：US15988375
申请日：2018-05-24
发明人： Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
IPC分类号： H01L29/76 , H01L29/66 , H01L21/306 , H01L21/02 , H01L29/10 , H01L29/165 , H01L29/08 , H01L29/423 , H01L29/06 , B82Y10/00 , H01L29/12
摘要： Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches. A gate structure is formed on the thin channel region.
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公开(公告)号：US10319847B2
公开(公告)日：2019-06-11
申请号：US15222324
申请日：2016-07-28
摘要： A method is presented for forming a semiconductor device. The method may include forming a source contact on the semiconductor substrate, forming a drain contact on the semiconductor substrate, and forming a gate structure on the semiconductor substrate between the source and drain contacts, the gate structure including a piezoelectric material having at least one graphene layer.
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