Planar metrology pad adjacent a set of fins of a fin field effect transistor device
    41.
    发明授权
    Planar metrology pad adjacent a set of fins of a fin field effect transistor device 有权
    平面计量垫相邻一组翅片场效应晶体管器件

    公开(公告)号:US09129905B2

    公开(公告)日:2015-09-08

    申请号:US14070624

    申请日:2013-11-04

    摘要: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

    摘要翻译: 公开了一种用于提供与翅片场效应晶体管(FinFET)器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除,例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模,并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去,允许在其中形成一组翅片,而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

    Planar metrology pad adjacent a set of fins of a fin field effect transistor device
    42.
    发明授权
    Planar metrology pad adjacent a set of fins of a fin field effect transistor device 有权
    平面计量垫相邻一组翅片场效应晶体管器件

    公开(公告)号:US09121890B2

    公开(公告)日:2015-09-01

    申请号:US14067204

    申请日:2013-10-30

    摘要: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

    摘要翻译: 公开了一种用于提供具有与翅片场效应晶体管(FinFET)器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说,FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模,在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂,在形成光致抗蚀剂之后,在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片,在FinFET器件上沉积氧化物层,以及平坦化FinFET器件,以形成平面度量板 计量测量领域。

    INTEGRATED CIRCUITS HAVING LATERALLY CONFINED EPITAXIAL MATERIAL OVERLYING FIN STRUCTURES AND METHODS FOR FABRICATING SAME
    43.
    发明申请
    INTEGRATED CIRCUITS HAVING LATERALLY CONFINED EPITAXIAL MATERIAL OVERLYING FIN STRUCTURES AND METHODS FOR FABRICATING SAME 有权
    具有横向限定的外来材料的整体电路,其结构和其制造方法

    公开(公告)号:US20150069515A1

    公开(公告)日:2015-03-12

    申请号:US14023558

    申请日:2013-09-11

    CPC分类号: H01L21/823431 H01L21/845

    摘要: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

    摘要翻译: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中,一种用于制造集成电路的方法包括提供覆盖半导体衬底的翅片结构。 翅片结构限定了在垂直于横向方向的纵向方向上延伸的翅片轴线,并且具有平行于翅片轴线的两个翅片侧壁。 该方法包括形成覆盖翅片结构并横向于翅片轴线的栅极结构。 此外,该方法包括在翅片结构上生长外延材料并限制外延材料在横向上的生长。