PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE
    1.
    发明申请
    PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE 有权
    平面计量垫附件一组熔点效应晶体管器件的FINS

    公开(公告)号:US20150123212A1

    公开(公告)日:2015-05-07

    申请号:US14070624

    申请日:2013-11-04

    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

    Abstract translation: 公开了一种用于提供与翅片场效应晶体管(FinFET)器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除,例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模,并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去,允许在其中形成一组翅片,而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

    PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE

    公开(公告)号:US20150115267A1

    公开(公告)日:2015-04-30

    申请号:US14067204

    申请日:2013-10-30

    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

    Systems and methods for fabricating semiconductor device structures using different metrology tools
    3.
    发明授权
    Systems and methods for fabricating semiconductor device structures using different metrology tools 有权
    使用不同计量工具制造半导体器件结构的系统和方法

    公开(公告)号:US08892237B2

    公开(公告)日:2014-11-18

    申请号:US13841919

    申请日:2013-03-15

    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.

    Abstract translation: 提供了用于制造和测量半导体器件结构的物理特征的方法和系统。 制造半导体器件结构的示例性方法包括从第一计量工具获得半导体器件结构的第一属性的第一测量,通过第一处理工具获得关于制造半导体器件结构的一个或多个特征的处理信息 并且至少部分地基于由所述处理信息影响的方式的所述第一测量来确定所述第一属性的调整的测量。

    Automating integrated circuit device library generation in model based metrology
    4.
    发明授权
    Automating integrated circuit device library generation in model based metrology 有权
    在基于模型的计量学中自动化集成电路设备库生成

    公开(公告)号:US08869081B2

    公开(公告)日:2014-10-21

    申请号:US13741645

    申请日:2013-01-15

    CPC classification number: H01L22/12 G03F7/70625 H01L2924/0002 H01L2924/00

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.

    Abstract translation: 各种实施例包括用于生成用于散射分析的集成电路(IC)库的计算机实现的方法,计算机程序产品和系统。 在某些情况下,方法包括:获得关于至少一个IC芯片的芯片设计数据; 获得关于所述至少一个IC芯片的用户输入数据; 并且使用其原始格式的芯片设计数据和其原始格式的用户输入数据运行IC库定义程序,IC库定义程序的运行包括:基于所述至少一个IC芯片确定所述至少一个IC芯片的处理变化 芯片设计数据和用户输入数据; 将过程变化转换为形状变化数据; 并将文本格式的形状变化数据提供给用于散射分析的散点建模程序。

    Three-dimensional scatterometry for measuring dielectric thickness

    公开(公告)号:US10508900B2

    公开(公告)日:2019-12-17

    申请号:US15870108

    申请日:2018-01-12

    Abstract: Methodologies and an apparatus for enabling three-dimensional scatterometry to be used to measure a thickness of dielectric layers in semiconductor devices are provided. Embodiments include initiating optical critical dimension (OCD) scatterometry on a three-dimensional test structure formed on a wafer, the three-dimensional test structure comprising patterned copper (Cu) trenches with an ultra-low k (ULK) dielectric film formed over the patterned Cu trenches; and obtaining, by a processor, a thickness of the ULK dielectric film based on results of the OCD scatterometry.

    HYBRID METROLOGY TECHNIQUE
    6.
    发明申请
    HYBRID METROLOGY TECHNIQUE 审中-公开
    混合计量技术

    公开(公告)号:US20170018069A1

    公开(公告)日:2017-01-19

    申请号:US15120692

    申请日:2014-10-30

    Abstract: A computerized system and method are provided for use in measuring at least one parameter of interest of a structure. The system comprises a server utility configured for data communication with at least first and second data provider utilities. The server utility receives, from the server provider utilities, measured data comprising first and second measured data pieces of different types indicative of parameters of the same structure; and is capable of processing the first and second measured data pieces for optimizing one or more first parameters values of the structure in one of the first and second measured data pieces by utilizing one or more second parameters values of the structure of the other of said first and second measured data pieces.

    Abstract translation: 提供了一种用于测量结构感兴趣的至少一个参数的计算机化系统和方法。 该系统包括配置用于与至少第一和第二数据提供者实用程序的数据通信的服务器实用程序。 服务器实用程序从服务器提供商实用程序接收包括指示相同结构的参数的不同类型的第一和第二测量数据段的测量数据; 并且能够通过利用所述第一和第二测量数据中的另一个的结构的一个或多个第二参数值来处理第一和第二测量数据,以优化第一和第二测量数据段之一中的结构的一个或多个第一参数值 和第二个测量数据。

    IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING
    7.
    发明申请
    IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING 审中-公开
    通过合理接地的现场有源波形充电屏蔽

    公开(公告)号:US20140073114A1

    公开(公告)日:2014-03-13

    申请号:US14077517

    申请日:2013-11-12

    Abstract: Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.

    Abstract translation: 本发明的实施例大体上涉及半导体晶片技术,更具体地,涉及在晶片处理和测量期间使用用于在晶片上进行有源电荷屏蔽的保形接地。 本发明的第一方面提供了一种减少半导体晶片上累积的表面电荷的方法,所述方法包括:使邻近晶片衬底的导电材料层接地; 并且允许在幅度上基本相等并且符号相反的镜像电荷与沿导电材料诱导的累积表面电荷。

    Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure
    9.
    发明授权
    Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure 有权
    对电路结构的多层的层厚进行去耦测量

    公开(公告)号:US09281249B2

    公开(公告)日:2016-03-08

    申请号:US14155504

    申请日:2014-01-15

    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

    Abstract translation: 获得电路结构层的厚度的测量,其中使用光学临界尺寸(OCD)测量技术测量层的厚度,并且层包括高k层和界面层。 分别获得高k层的厚度的测量,其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比,单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性,如界面层的厚度,部分使用单独获得的高k层的厚度测量来确定。

    Planar metrology pad adjacent a set of fins of a fin field effect transistor device
    10.
    发明授权
    Planar metrology pad adjacent a set of fins of a fin field effect transistor device 有权
    平面计量垫相邻一组翅片场效应晶体管器件

    公开(公告)号:US09129905B2

    公开(公告)日:2015-09-08

    申请号:US14070624

    申请日:2013-11-04

    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

    Abstract translation: 公开了一种用于提供与翅片场效应晶体管(FinFET)器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除,例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模,并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去,允许在其中形成一组翅片,而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

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