公开(公告)号：US07632728B2

公开(公告)日：2009-12-15

申请号：US12232080

申请日：2008-09-10

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

公开(公告)号：US07601623B2

公开(公告)日：2009-10-13

申请号：US12219096

申请日：2008-07-16

申请人： Yoshinori Tsuchiya ,  Masato Koyama

发明人： Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4958 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665

摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

摘要翻译： 半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。 栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。 源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。 元件分离绝缘膜层围绕半导体层。 布线与栅电极的金属或金属化合物接触。

公开(公告)号：US07569891B2

公开(公告)日：2009-08-04

申请号：US11709857

申请日：2007-02-23

申请人： Yoshinori Tsuchiya ,  Masato Koyama

发明人： Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor substrate so as to separate each other, each including: a silicide layer containing a first metal element as a main component having a vacuum work function of 4.6 eV or greater; and a layer containing at least one second metal element selected from the group of scandium elements and lanthanoid, the layer containing the second metal element including a segregating layer in which the highest areal density is 1×1014 cm−2 or higher, each region of the segregating layer with areal density of 1×1014 cm−2 or higher having a thickness smaller than 1 nm; a gate insulating film provided a region between the source and drain regions on the semiconductor substrate; and a gate electrode provided on the gate insulating film.

摘要翻译： 可以降低n型MISFET中的源极和漏极的接触电阻。 半导体器件包括：源区和漏区，设置在p型半导体衬底中以彼此分离，每个包括：含有第一金属元素作为主要成分的硅化物层，其真空功函数为4.6eV或更大 ; 以及包含选自钪元素和镧系元素的至少一种第二金属元素的层，所述第二金属元素的层包含其中最高面密度为1×10 14 cm -2以上的偏析层，所述偏析层的每个区域 层，其面密度为1×10 14 cm -2以上，厚度小于1nm; 栅绝缘膜设置在半导体衬底上的源区和漏区之间的区域; 以及设置在栅极绝缘膜上的栅电极。

公开(公告)号：US20090114995A1

公开(公告)日：2009-05-07

申请号：US12200599

申请日：2008-08-28

申请人： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

发明人： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

IPC分类号： H01L27/08 ,  H01L21/3205

CPC分类号： H01L21/823857 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/785

摘要： A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

摘要翻译： 互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管 形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管， 以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

公开(公告)号：US20090075464A1

公开(公告)日：2009-03-19

申请号：US12232080

申请日：2008-09-10

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L21/28

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

公开(公告)号：US20090072330A1

公开(公告)日：2009-03-19

申请号：US12232078

申请日：2008-09-10

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/78

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

公开(公告)号：US07432570B2

公开(公告)日：2008-10-07

申请号：US11635040

申请日：2006-12-07

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

公开(公告)号：US20080237727A1

公开(公告)日：2008-10-02

申请号：US11965563

申请日：2007-12-27

申请人： Reika ICHIHARA ,  Yoshinori Tsuchiya ,  Masato Koyama

发明人： Reika ICHIHARA ,  Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： The present invention provides a CMIS device that achieves a low threshold voltage by use of a metal gate superior in the resistance to annealing in a reducing atmosphere. The CMIS device includes a substrate, PMISFET and NMISFET. THE PMISFET includes: an N-type semiconductor layer formed on the substrate; first source/drain regions formed in the N-type semiconductor layer; a first gate insulating film formed on the N-type semiconductor layer between the first source/drain regions; a carbon layer formed on the first gate insulating film and having a thickness of 5 nanometers or smaller; a first gate electrode formed on the carbon layer and including a metal.

摘要翻译： 本发明提供了一种CMIS器件，其通过使用在还原气氛中的退火电阻优异的金属栅极来实现低阈值电压。 CMIS器件包括衬底，PMISFET和NMISFET。 PMISFET包括：形成在衬底上的N型半导体层; 形成在N型半导体层中的第一源/漏区; 形成在所述第一源极/漏极区域之间的所述N型半导体层上的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上并具有5纳米或更小的厚度的碳层; 形成在碳层上并包括金属的第一栅电极。

公开(公告)号：US20070001238A1

公开(公告)日：2007-01-04

申请号：US11355132

申请日：2006-02-16

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Reika Ichihara

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Reika Ichihara

IPC分类号： H01L29/76

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.

公开(公告)号：US20060289863A1

公开(公告)日：2006-12-28

申请号：US11472449

申请日：2006-06-22

申请人： Ryosuke Iijima ,  Masato Koyama

发明人： Ryosuke Iijima ,  Masato Koyama

IPC分类号： H01L23/58

CPC分类号： G01R31/2621 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected to a first source/drain region of the field-effect transistor. The switch can be electrically connected to a second source/drain region of the field-effect transistor. The switch switches between a connection state and a disconnection state. The first constant-voltage source can be electrically connected to the second source/drain region through the switch.

摘要翻译： 用于评估场效应晶体管的装置包括脉冲发生器，电流/电压转换器，开关和第一恒压源。 脉冲发生器可以电连接到场效应晶体管的栅电极。 电流/电压转换器包括输入端子。 输入端子可以电连接到场效应晶体管的第一源极/漏极区域。 开关可以电连接到场效应晶体管的第二源/漏区。 交换机在连接状态和断开状态之间切换。 第一恒压源可以通过开关电连接到第二源极/漏极区域。