中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

106 records (took 0.036 seconds)

    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
    44.
    发明授权
    Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权

    公开(公告)号：US10042639B2

    公开(公告)日：2018-08-07

    申请号：US15397678

    申请日：2017-01-03

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: G06F9/00 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F7/544

    Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

    Look-ahead hash chain matching for data compression
    46.
    发明授权
    Look-ahead hash chain matching for data compression 有权

    公开(公告)号：US09768802B2

    公开(公告)日：2017-09-19

    申请号：US15406133

    申请日：2017-01-13

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/00 ,  H03M7/30 ,  H03M7/42

    CPC classification number: H03M7/3086 ,  H03M7/42

    Abstract: Example data compression methods disclosed herein include determining a first hash chain index corresponding to a first position in an input data buffer based on a first group of bytes accessed from the input data buffer beginning at a first look-ahead offset from the first position. If a first hash chain (indexed by the first hash chain index), does not satisfy a quality condition, a second hash chain index corresponding to the first position in the input data buffer based on a second group of bytes accessed from the input data buffer beginning at a second look-ahead offset from the first position is determined. The input data buffer is searched at respective adjusted buffer positions to find a second string of data bytes matching a first string of data bytes and information related to the second string of data bytes is provided to an encoder to output compressed data.

    INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY
    49.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY 审中-公开

    公开(公告)号：US20160373250A1

    公开(公告)日：2016-12-22

    申请号：US14568101

    申请日：2014-12-11

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

    IPC: H04L9/06 ,  G06F9/38

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

    Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

    Generating multiple secure hashes from a single data buffer
    50.
    发明授权
    Generating multiple secure hashes from a single data buffer 有权
    从单个数据缓冲区生成多个安全散列

    公开(公告)号：US09425953B2

    公开(公告)日：2016-08-23

    申请号：US14050326

    申请日：2013-10-09

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Vinodh Gopal ,  Wajdi K. Feghali ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

    IPC: H04L9/06

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要 至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

Patent Agency Ranking