公开(公告)号：US20050020086A1

公开(公告)日：2005-01-27

申请号：US10730996

申请日：2003-12-10

申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311

CPC分类号： H01L29/66553 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

公开(公告)号：US06562697B1

公开(公告)日：2003-05-13

申请号：US10093295

申请日：2002-03-07

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06242332B1

公开(公告)日：2001-06-05

申请号：US09384281

申请日：1999-08-27

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

IPC分类号： H01L213205

CPC分类号： H01L21/76897

摘要： The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

摘要翻译： 本发明的焊盘的尺寸减小，从而防止聚合物蚀刻停止，从而抑制由覆盖栅极导电层的氧化物层的损坏而露出的栅极和栅极导电层之间的短路，并且延伸顶表面 超过照相设备的技术限制的垫的面积。 结果，可以极大地确保电连接到焊盘的埋入触点的对准。

公开(公告)号：US6136657A

公开(公告)日：2000-10-24

申请号：US315341

申请日：1999-05-20

申请人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/423 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42368 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/28211 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/981

摘要： A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.

摘要翻译： 提供一种制造具有不同栅氧化层的半导体器件的方法。 在该方法中，根据有源面积尺寸控制氧化，使得氧化物在周边区域中以更宽的有源宽度更薄地生长，并且在单元阵列区域中以较窄的有源宽度生长更厚。 在该方法中，在具有不同有源区域的半导体衬底上形成栅极图案。 形成栅极间隔物，然后执行活性尺寸依赖性氧化工艺以在电池阵列区域和外围区域中生长不同厚度的氧化物层。