公开(公告)号：US07888198B1

公开(公告)日：2011-02-15

申请号：US09313659

申请日：1999-05-18

申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。

公开(公告)号：US6136657A

公开(公告)日：2000-10-24

申请号：US315341

申请日：1999-05-20

申请人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/423 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42368 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/28211 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/981

摘要： A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.

摘要翻译： 提供一种制造具有不同栅氧化层的半导体器件的方法。 在该方法中，根据有源面积尺寸控制氧化，使得氧化物在周边区域中以更宽的有源宽度更薄地生长，并且在单元阵列区域中以较窄的有源宽度生长更厚。 在该方法中，在具有不同有源区域的半导体衬底上形成栅极图案。 形成栅极间隔物，然后执行活性尺寸依赖性氧化工艺以在电池阵列区域和外围区域中生长不同厚度的氧化物层。

公开(公告)号：US06768148B1

公开(公告)日：2004-07-27

申请号：US10403480

申请日：2003-03-31

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2976

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06753227B2

公开(公告)日：2004-06-22

申请号：US10437881

申请日：2003-05-13

申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

IPC分类号： H01L21336

CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

公开(公告)号：US06562697B1

公开(公告)日：2003-05-13

申请号：US10093295

申请日：2002-03-07

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06242332B1

公开(公告)日：2001-06-05

申请号：US09384281

申请日：1999-08-27

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

IPC分类号： H01L213205

CPC分类号： H01L21/76897

摘要： The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

摘要翻译： 本发明的焊盘的尺寸减小，从而防止聚合物蚀刻停止，从而抑制由覆盖栅极导电层的氧化物层的损坏而露出的栅极和栅极导电层之间的短路，并且延伸顶表面 超过照相设备的技术限制的垫的面积。 结果，可以极大地确保电连接到焊盘的埋入触点的对准。

公开(公告)号：US07701235B2

公开(公告)日：2010-04-20

申请号：US12098778

申请日：2008-04-07

申请人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

发明人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

IPC分类号： G01R31/02

CPC分类号： G01R31/2889 ,  G01R31/2891

摘要： Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.

摘要翻译： 具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法，其中用于探针卡的受力图案和用于测试头的强制部件 当在高温和低温下测试半导体衬底时，可以抑制探针卡的热膨胀和收缩。 为此，制备具有基板移动器，探针卡和测试头的基板测试探测设备，其中测试头具有强制部分，探针卡具有受力板。 将半导体衬底放置在衬底移动器上以与探针卡电连接。 半导体衬底由探针卡和测试头电测试。 当半导体衬底被测试时，测试头的强制部分与探针卡的受力图案接触。

公开(公告)号：US07180118B2

公开(公告)日：2007-02-20

申请号：US10830895

申请日：2004-04-22

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US5844914A

公开(公告)日：1998-12-01

申请号：US850807

申请日：1997-05-02

申请人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

发明人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/3181 ,  G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/18 ,  G01R31/31813

摘要： A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

摘要翻译： 示出了半导体存储器件和方法，其中内置系统测试（BIST）电路基于测试算法和DRAM存储单元阵列的刷新要求确定BIST电路执行刷新操作的刷新点地址 当测试地址到达刷新点地址时，在存储单元阵列中的测试数据。 还示出了半导体存储器件和方法的另一实施例，其中BIST电路在输入到存储器电路之前对测试地址和测试数据进行解扰，该存储器电路包括地址和数据加扰电路，使得逻辑测试地址和根据 测试算法与存储单元阵列中的物理地址和数据相匹配。

公开(公告)号：US20110128022A1

公开(公告)日：2011-06-02

申请号：US12798605

申请日：2010-04-07

申请人： Jae-Young Choi ,  Chang-Hyun Cho

发明人： Jae-Young Choi ,  Chang-Hyun Cho

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/3187

CPC分类号： G01R31/318511

摘要： A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

摘要翻译： 测试装置包括：测试控制器，被配置为从多个芯片中输出用于选择要测试的芯片的多个芯片选择信号;多个第一控制信号，用于控制向由芯片选择的芯片提供的电源电压 选择信号和多个第二控制信号，用于控制从提供有电源电压的芯片输出的测试电压的接收;以及探针卡，其包括一个或多个测试块，每个测试块具有多个信号发射机，其被配置为分别传输功率 响应于不同的第一控制信号向相应的芯片提供电压，并且响应于不同的第二控制信号分别将从相应芯片输出的测试电压施加到测试控制器。