公开(公告)号：US06768148B1

公开(公告)日：2004-07-27

申请号：US10403480

申请日：2003-03-31

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2976

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06562697B1

公开(公告)日：2003-05-13

申请号：US10093295

申请日：2002-03-07

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US07888198B1

公开(公告)日：2011-02-15

申请号：US09313659

申请日：1999-05-18

申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。

公开(公告)号：US06753227B2

公开(公告)日：2004-06-22

申请号：US10437881

申请日：2003-05-13

申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

IPC分类号： H01L21336

CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

公开(公告)号：US06242332B1

公开(公告)日：2001-06-05

申请号：US09384281

申请日：1999-08-27

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Ki-Nam Kim

IPC分类号： H01L213205

CPC分类号： H01L21/76897

摘要： The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

摘要翻译： 本发明的焊盘的尺寸减小，从而防止聚合物蚀刻停止，从而抑制由覆盖栅极导电层的氧化物层的损坏而露出的栅极和栅极导电层之间的短路，并且延伸顶表面 超过照相设备的技术限制的垫的面积。 结果，可以极大地确保电连接到焊盘的埋入触点的对准。

公开(公告)号：US6136657A

公开(公告)日：2000-10-24

申请号：US315341

申请日：1999-05-20

申请人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/423 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42368 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/28211 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/981

摘要： A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.

摘要翻译： 提供一种制造具有不同栅氧化层的半导体器件的方法。 在该方法中，根据有源面积尺寸控制氧化，使得氧化物在周边区域中以更宽的有源宽度更薄地生长，并且在单元阵列区域中以较窄的有源宽度生长更厚。 在该方法中，在具有不同有源区域的半导体衬底上形成栅极图案。 形成栅极间隔物，然后执行活性尺寸依赖性氧化工艺以在电池阵列区域和外围区域中生长不同厚度的氧化物层。

公开(公告)号：US20130345464A1

公开(公告)日：2013-12-26

申请号：US14003276

申请日：2012-02-22

申请人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

发明人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

IPC分类号： C07F9/09

CPC分类号： C07F9/091

摘要： The present invention relates to I- and II-type crystals of L-α-glyceryl phosphoryl choline, and to a method for preparing same. More particularly, the present invention relates to noble I- and II-type anhydride crystals of L-α-glyceryl phosphoryl choline, which have a higher purity than conventional liquid L-α-glyceryl phosphoryl choline, and one advantage of which is that formulations and dosages of pharmaceuticals are easily modified, and another advantage of which is that the hygroscopicity of the crystals are much lower than that of conventional polymorphic crystals, providing excellent stability during storage. The present invention also relates to a method for preparing the I- and II-type crystals of L-α-glyceryl phosphoryl choline.

摘要翻译： 本发明涉及L-α-甘油磷酰胆碱的I型和II型晶体及其制备方法。 更具体地，本发明涉及具有比常规液体L-α-甘油磷酰胆碱更高纯度的L-α-甘油磷酰胆碱的高级I型和II型酸酐晶体，其优点之一是制剂 并且药物的剂量容易改性，其另一个优点是结晶的吸湿性远低于常规多晶型晶体的吸湿性，在储存期间提供极好的稳定性。 本发明还涉及一种制备L-α-甘油磷酰胆碱的I型和II型晶体的方法。

公开(公告)号：US08026504B2

公开(公告)日：2011-09-27

申请号：US12379814

申请日：2009-03-02

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

公开(公告)号：US07888667B2

公开(公告)日：2011-02-15

申请号：US12008125

申请日：2008-01-09

申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

IPC分类号： H01L47/00 ,  H01L21/00 ,  G11C11/00

CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

公开(公告)号：US20100330752A1

公开(公告)日：2010-12-30

申请号：US12842703

申请日：2010-07-23

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/322 ,  H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。