公开(公告)号：US20050182990A1

公开(公告)日：2005-08-18

申请号：US11070843

申请日：2005-02-24

申请人： Markus Gail ,  Jan Otterstedt

发明人： Markus Gail ,  Jan Otterstedt

IPC分类号： G06F11/00 ,  G06F21/00

CPC分类号： G06F21/71 ,  G06F9/321 ,  G06F9/3861 ,  G06F21/52 ,  G06F21/77

摘要： Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

摘要翻译： 具有执行单元的数据处理装置，具有程序计数器的流量控制器和程序计数器传感器，其连接到数据总线和程序计数器。 程序计数器传感器具有逻辑单元，该逻辑单元确定下一个将经由数据总线传送的数据执行的指令的地址;以及比较器，其将确定的地址与程序计数器的内容进行比较，并触发报警信号 如果有任何差异。

公开(公告)号：US08533557B2

公开(公告)日：2013-09-10

申请号：US13016308

申请日：2011-01-28

申请人： Jan Otterstedt ,  Rainer Goettfert

发明人： Jan Otterstedt ,  Rainer Goettfert

IPC分类号： H03M13/00

CPC分类号： H03M13/2942 ,  H03M13/13 ,  H03M13/2906 ,  H03M13/3715

摘要： A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cvA associated with a data word a so that cvA=aAT, with A being a generator matrix of a linear systematic base correction code, the columns of which enable performance of an x-bit error correction on replica of the data word a and the associated error correction code cvA. The second determiner is configured to determine an extended error correction code cvE so that (cvA|cvE)=aFT, with F being an extended generator matrix F = ( A E ) of an extended linear systematic correction code, the columns of which enable, using the extension error correction code cvE, performance of an y-bit error correction, with y>x, on a replica of the data word a and the associated error correction code cvA.

摘要翻译： 用于保护数据字免受数据损坏的设备包括第一和第二确定器。 第一确定器被配置为确定与数据字a相关联的纠错码cvA，使得cvA = aAT，其中A是线性系统基本校正码的生成矩阵，其列允许执行x位错误 对数据字a和相关纠错码cvA的副本进行校正。 第二确定器被配置为确定扩展误差校正码cvE，使得（cvA | cvE）= aFT，其中F是扩展的线性系统校正码的扩展生成矩阵F =（AE），其列允许使用 扩展误差校正码cvE，在数据字a和相关联的纠错码cvA的副本上执行具有y> x的y位纠错的性能。

公开(公告)号：US08509007B2

公开(公告)日：2013-08-13

申请号：US13405523

申请日：2012-02-27

申请人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Nigel Chan ,  Jan Otterstedt

IPC分类号： G11C7/06 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G06T7/223 ,  G06T2207/10016 ,  G06T2207/20016 ,  G06T2207/20021 ,  G11C2211/5634 ,  H04N19/53

摘要： Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.

摘要翻译： 本公开的一些方面涉及使用如本文所阐述的混合读取方案的读取电路。 在该混合读取方案中，状态机在读取操作中的第一时间将参考信号SRef设置为第一参考值以引起第一比较结果的确定。 在读取操作的第二随后时间，状态机将参考信号SRef设置为基于第一比较结果的第二参考值。 将参考信号设置为第二参考值引起第二比较结果的确定。 然后使用第一和第二比较结果来确定从存储器单元读取的数字值。

公开(公告)号：US20110194364A1

公开(公告)日：2011-08-11

申请号：US12702759

申请日：2010-02-09

申请人： Thomas Nirschl ,  Christoph Bukethal ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Christoph Bukethal ,  Jan Otterstedt

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C16/10 ,  G11C8/08

摘要： The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time.

摘要翻译： 所公开的发明提供了一种用于增加操作速度并减少存储器阵列的整体编程时间的结构和方法。 在一个实施例中，本文提供的方法和结构通过在不同时间写入共享激活字线的数据位（例如，激活与...相关联的位线）来减少用于将多个数据位写入NVM阵列的最大写入电流消耗 在不同时间激活字线）。 具体地说，分别仅使用比特的整个写入窗口的一部分的各个数据比特的写入操作被交织，使得各个比特的最大写入电流在时间上偏离另一个比特的最大写入电流。 数据位写入窗口的这种交错允许在不超出系统规格（例如，最大电流））的情况下写入更大数量的数据位，从而减少总体存储器写入时间。

公开(公告)号：US07739520B2

公开(公告)日：2010-06-15

申请号：US10638659

申请日：2003-08-11

申请人： Helmut Horvat ,  Jan Otterstedt ,  Stefan Wallstab

发明人： Helmut Horvat ,  Jan Otterstedt ,  Stefan Wallstab

IPC分类号： G06F12/14

CPC分类号： H04N21/6334 ,  G06F15/7867 ,  G06F21/32 ,  G06F21/72 ,  G06F21/77 ,  H04N21/4181 ,  H04N21/4405

摘要： The invention relates to a data processing device with a functionally programmable logic circuit and a programming interface. An authorization control unit is provided, which protects the programming interface against an unauthorized access. This enables the functions of a semiconductor module to be changed in a customer-specific manner while preventing unauthorized entities from subsequently changing the functionality.

摘要翻译： 本发明涉及具有功能可编程逻辑电路和编程接口的数据处理装置。 提供授权控制单元，其保护编程接口免受未经授权的访问。 这使得可以以客户特定的方式改变半导体模块的功能，同时防止未经授权的实体随后改变功能。

公开(公告)号：US07634640B2

公开(公告)日：2009-12-15

申请号：US11070843

申请日：2005-02-24

申请人： Markus Gail ,  Jan Otterstedt

发明人： Markus Gail ,  Jan Otterstedt

IPC分类号： G06F9/44

CPC分类号： G06F21/71 ,  G06F9/321 ,  G06F9/3861 ,  G06F21/52 ,  G06F21/77

摘要： Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

摘要翻译： 具有执行单元的数据处理装置，具有程序计数器的流量控制器和程序计数器传感器，其连接到数据总线和程序计数器。 程序计数器传感器具有逻辑单元，该逻辑单元确定下一个将经由数据总线传送的数据执行的指令的地址;以及比较器，其将确定的地址与程序计数器的内容进行比较，并触发报警信号 如果有任何差异。

公开(公告)号：US07552273B2

公开(公告)日：2009-06-23

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US20080239833A1

公开(公告)日：2008-10-02

申请号：US11731766

申请日：2007-03-30

申请人： Thomas Nirschl ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Jan Otterstedt

IPC分类号： G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

摘要： A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

摘要翻译： 多级感测方案将多级存储单元的状态与单调变化的参考状态进行比较，其与不同的信息值相关联。 该特定信息值被识别为存储在多级存储单元中的信息，其与改变方向上首先超过该状态的参考状态相关联。

公开(公告)号：US20080126717A1

公开(公告)日：2008-05-29

申请号：US11555799

申请日：2006-11-02

申请人： Jan Otterstedt ,  Holger Sedlak

发明人： Jan Otterstedt ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G11C16/3418 ,  G11C16/3431

摘要： A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

摘要翻译： 一种具有多个存储区域的存储器电路，其顺序依赖于分别相关的逻辑地址，并且每个存储区域具有相关联的控制值，以及控制装置，其被设计为使得其相应于与 当存在时，对应于最低使用存储区域的值的目标存储区域，当存在时，分配相同的任意或预定值，当不存在时，以及当满足预定条件时，以及当处于 存在至少两个使用的存储区域，重写其控制值与最低存储区域的控制值具有预定关系的下一个存储区域的内容，并且改变该存储区域的控制值，当存在​​该存储区域的存储区域存在时，或者重写 最低存储器区域的内容并且改变相关联的控制值，当下一个存储区域的控制值与最低存储器ar的控制值具有预定的关系时 ea，不存在。

公开(公告)号：US20050270061A1

公开(公告)日：2005-12-08

申请号：US11147414

申请日：2005-06-06

申请人： Jan Otterstedt

发明人： Jan Otterstedt

IPC分类号： G06F12/14 ,  G06F15/78 ,  G06F21/75 ,  H03K19/173 ,  H03K19/177 ,  H04L12/22

CPC分类号： H03K19/17768 ,  G06F21/755 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/17732

摘要： A configurable logic circuit having a plurality of logic blocks and a connecting structure, via which the logic blocks are interconnectable, wherein the logic blocks are implemented in dual rail technique.

摘要翻译： 具有多个逻辑块和连接结构的可配置逻辑电路，逻辑块经由该连接结构可互连，其中逻辑块以双轨技术实现。