公开(公告)号：US20050144553A1

公开(公告)日：2005-06-30

申请号：US11045634

申请日：2005-01-28

申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

IPC分类号： G06F17/30 ,  G06F17/00

CPC分类号： G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

公开(公告)号：US20050076010A1

公开(公告)日：2005-04-07

申请号：US10650327

申请日：2003-08-28

申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

IPC分类号： G06F17/30 ,  H04L12/46 ,  H04L12/56 ,  G06F7/00

CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBS) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 输入密钥，对密钥执行散列函数，访问直接表（DT），并通过模式搜索控制块（PSCBS）走树，直到到达叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

公开(公告)号：US5444692A

公开(公告)日：1995-08-22

申请号：US161372

申请日：1993-12-02

申请人： Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

发明人： Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

IPC分类号： H04L12/433 ,  H04L12/56 ,  H04L12/417

CPC分类号： H04L12/433 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351

摘要： The invention includes a bridge having n ports (n>1), each port being connected to a Token-Ring physical segment, each physical segment having one native Token-Ring workstation attached. The bridge to the workstations a single Token-Ring logical segment with a single Active Monitor and a single Ring Number. The invention includes a centralized medium access control (MAC) function inside a centralized processor instead of a MAC function implemented at each port of the bridge; the frame handling function, due to the fixed and limited configuration (same bridge Active Monitor seen by all connected stations), does not require a multi-port bridge function, but a simpler switch function between ports. Bridge clocking is also simplified, and a cost effective unshield twisted pair (UTP) retiming solution is presented.

摘要翻译： 本发明包括具有n个端口（n> 1）的桥，每个端口连接到令牌环物理段，每个物理段具有一个本地令牌环工作站。 工作站的桥接到单个活动监视器和单个环号的单个令牌环逻辑段。 本发明包括集中式处理器内的中央媒体访问控制（MAC）功能，而不是在桥的每个端口处实现的MAC功能; 帧处理功能由于固定和限制配置（所有连接站所见的同一桥主动监视器）不需要多端口桥接功能，而是端口之间更简单的交换机功能。 桥接时钟也被简化，并提出了一种经济有效的非屏蔽双绞线（UTP）重新定时器解决方案。

公开(公告)号：US20120195208A1

公开(公告)日：2012-08-02

申请号：US13017963

申请日：2011-01-31

申请人： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

发明人： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

IPC分类号： H04L12/26 ,  H04J3/24

CPC分类号： H04L69/22

摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.

摘要翻译： 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

公开(公告)号：US20080046797A1

公开(公告)日：2008-02-21

申请号：US11875995

申请日：2007-10-22

申请人： James Allen ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

发明人： James Allen ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

IPC分类号： H03M13/09

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L12/5601 ,  H04L45/742 ,  H04L2012/5627 ,  H04L2012/5656

摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.

摘要翻译： 用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC生成器使用2.sup.16位来生成第二个CRC表。 通过将CID字段，LI字段和UUI字段中的位与两个表相关来生成特定CPS头的CRC。

公开(公告)号：US20050232270A1

公开(公告)日：2005-10-20

申请号：US11152699

申请日：2005-06-14

申请人： Brian Bass ,  Jean Calvignac ,  Anthony Gallo ,  Marco Heddes ,  Sridhar Rao ,  Michael Siegel ,  Brian Youngman ,  Fabrice Verplanken

发明人： Brian Bass ,  Jean Calvignac ,  Anthony Gallo ,  Marco Heddes ,  Sridhar Rao ,  Michael Siegel ,  Brian Youngman ,  Fabrice Verplanken

IPC分类号： G06F15/16 ,  G06F13/40 ,  G06F15/177 ,  H04L12/56

CPC分类号： H04L49/3036 ,  G06F13/4022 ,  H04L49/15 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351

摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：US06370148B1

公开(公告)日：2002-04-09

申请号：US09110920

申请日：1998-07-06

申请人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Gilles Toubol

发明人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Gilles Toubol

IPC分类号： H04J314

CPC分类号： H04L49/106 ,  H04L49/20 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/508

摘要： An improved arbiter is described for arbitrating requests by a plurality of first data processing units for access to a plurality of second data processing units interconnected by a switching system of a type in which at any time each first unit can only access one second unit and each second unit can only be accessed by one first unit. The arbiter comprises a scheduler mechanism for repeatedly selecting access requests with a defined minimum probability of selecting a request for each first unit-second unit combination. Rearrangement storage means records requests selected by the scheduler mechanism. A rearranger is provided for repeatedly selecting a set of requests recorded in the rearrangement storage means, so that only one request per first unit and per second unit is selected, using a priority mechanism which increases the probability of selection with the length of time a request is stored in the rearrangement storage means. Finally, means are provided for communicating the grant of the selected set of requests to the switching system and for deleting the selected set of requests from the rearrangement storage means. In one embodiment, the arbiter is used for controlling switching paths in a packet data switch.

摘要翻译： 描述了一种改进的仲裁器，用于对多个第一数据处理单元的请求进行仲裁，以访问多个第二数据处理单元，该多个第二数据处理单元通过一种类型的交换系统互连，其中每个第一单元在任何时候只能访问一个第二单元，并且每个 第二单元只能由一个第一单元访问。 仲裁器包括一个调度机制，用于以对每个第一单位 - 第二单位组合选择一个请求的限定的最小概率重复地选择访问请求。 重排存储装置记录由调度机制选择的请求。 提供了一种重排器，用于重复选择记录在重排存储装置中的一组请求，使得仅使用优先级机制选择每第一单元和每秒单元的一个请求，该优先级机制随着请求的长度增加选择的概率 存储在重排存储装置中。 最后，提供了用于将所选择的一组请求的许可传送给交换系统并且用于从重排存储装置中删除所选择的一组请求的装置。 在一个实施例中，仲裁器用于控制分组数据交换机中的交换路径。

公开(公告)号：US5787071A

公开(公告)日：1998-07-28

申请号：US554113

申请日：1995-11-06

申请人： Claude Basso ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

发明人： Claude Basso ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/563 ,  H04L2012/5632 ,  H04L2012/5635 ,  H04L2012/5636 ,  H04L2012/5651 ,  H04L2012/5652

摘要： A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.

摘要翻译： 通信系统包括通过包括多个连接的链路互连的多个节点。 节点之间的流量由保留的带宽服务和/或非保留带宽服务建立。 非保留带宽服务由逐跳背压机制控制。 当进入节点的流量超过高阈值时，背压机制产生停止背压原语，以节流输入流量。 在拥塞的情况下，该机制能够选择性地插入有助于拥塞的连接而不影响链路业务的其余部分，或全局地停止所有链路业务。 如果流量低于低阈值，流量可以恢复。

公开(公告)号：US5687356A

公开(公告)日：1997-11-11

申请号：US579555

申请日：1995-12-27

申请人： Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

发明人： Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

IPC分类号： G06F13/00 ,  H04L7/00 ,  H04L12/433 ,  H04L12/64 ,  G06F9/00

CPC分类号： H04L12/6418 ,  H04L12/433 ,  H04L2012/6437 ,  H04L2012/6451 ,  H04L2012/6454 ,  H04L2012/6459

摘要： A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46). The switch and other concentration logic receive a hub local clock (412). Isochronous traffic interchanges with the hub backplane through leads 410 and 411; between ports or between ports and the hub through leads 407 and 409. Data to a connected station is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

摘要翻译： 具有用于将站附接到LAN的端口的集线器包括用于处理复用的进入和输出令牌环和等时信号流的集中逻辑（14）。 浓度逻辑包括来自输入令牌环分组数据流（40）的时钟恢复逻辑（42），用于在输出（400）上再生差分曼彻斯特编码数据，以及恢复令牌环时钟（401）。 周期成帧发生器（43）从集线器背板（402）和令牌环时钟（401）接收125 us同步时钟，并产生到10个端口中的每一个的控制信号（403）。 每个端口由端口传输接口（44）和端口接收接口（45）组成。 来自连接站的数据被输入（404）到端口接收接口（45）。 令牌环包差分曼彻斯特编码数据输出（406）到下一个有效端口，特别是与其恢复的选通时钟（405）一起输出到其端口传输接口，同时将ISO数据输出（407）转换为开关（46）。 交换机和其他集中逻辑接收集线器本地时钟（412）。 通过引线410和411与轮毂底板进行同步通信交换; 通过引线407和409在端口之间或端口之间以及集线器之间。从端口传输接口（44）输出到连接站的数据（408）。 接收差分曼彻斯特编码数据（400）以及令牌环时钟（401）。 控制信号被输入（403）。 接收同步数据（409）。 令牌环包差分曼彻斯特编码数据最终从浓度逻辑输出（41）。

公开(公告)号：US5668798A

公开(公告)日：1997-09-16

申请号：US547827

申请日：1995-10-25

申请人： Gilles Toubol ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Luc Torres ,  Fabrice Verplanken

发明人： Gilles Toubol ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Luc Torres ,  Fabrice Verplanken

IPC分类号： H04L12/70 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5616

摘要： A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.

摘要翻译： 诸如ATM或异步传输模式开关的数据交换设备包括具有多个输入和输出引线的交换结构。 该设备还包括至少一个用于在多个输入端口中的每一个上接收数据单元的输入适配器和至少一个输出适配器，用于将通过交换结构交换的数据单元传送到一组输出端口中的目标端口。 在进入的单元格上执行错误和格式检查，并且保留在特定输入端口上接收到的良好单元和无效单元的数量的计数。 为了降低硬件成本，将计数保存在随机存取存储器中，该存储器在输入端口之间共享。 将几个存储位置分配给每个输入端口以维持必要的计数。