公开(公告)号：US08513663B2

公开(公告)日：2013-08-20

申请号：US12754054

申请日：2010-04-05

申请人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

发明人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： G01R31/2889 ,  G01R31/318513 ,  H01L2924/0002 ,  Y10T307/492 ,  H01L2924/00

摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

摘要翻译： 一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

公开(公告)号：US07865855B2

公开(公告)日：2011-01-04

申请号：US11942744

申请日：2007-11-20

申请人： Juergen Koehl ,  Matthias Ringe

发明人： Juergen Koehl ,  Matthias Ringe

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068

摘要： A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source is disclosed. The source supplies a plurality of signals to the respective plurality of sinks. The method includes: identifying the source which supplies at least one of the respective sinks and having a negative slack; finding all sinks having a negative slack driven by the source; clustering the sinks according to timing and placement information read from a database, yielding a plurality of clusters of sinks, in which each cluster includes only a predetermined portion of the plurality of sinks; generating a plurality of clones associated with a respective one of the clusters of sinks; and coupling the clones to respective ones of the clusters of sinks yielding a second layout.

摘要翻译： 公开了一种用于产生具有多个接收器和至少一个源的集成电路的布局的方法。 源将多个信号提供给相应的多个汇。 该方法包括：识别供应相应汇的至少一个并且具有负的松弛的源; 找到由源驱动的负松弛的所有水槽; 根据从数据库读取的定时和放置信息来聚集汇，产生多个汇集群，其中每个群只包括多个汇的预定部分; 产生与所述汇的簇中的相应一个相关联的多个克隆; 并将克隆耦合到汇的各个簇中，产生第二布局。

公开(公告)号：US20100257503A1

公开(公告)日：2010-10-07

申请号：US12417136

申请日：2009-04-02

申请人： Markus Buehler ,  Michael A. Kazda ,  Juergen Koehl

发明人： Markus Buehler ,  Michael A. Kazda ,  Juergen Koehl

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for rerouting a wire in an integrated circuit includes determining a wire coupling a first circuit element to a second circuit element is experiencing capacitive coupling effects with one or more other wires; removing the wire from a netlist; dividing the structure into a routing grid; defining a first and second wire types; associating a penalty with each wire type; determining all possible paths through the routing grid between the first circuit element and the second circuit element; determining a weighted length for each path; and selecting the path having the lowest weighted length.

摘要翻译： 一种用于在集成电路中重新布线的方法包括确定将第一电路元件连接到第二电路元件的线耦合正在经历与一个或多个其它线的电容耦合效应; 从网表中取出电线; 将结构划分为路由网格; 定义第一和第二线类型; 将罚款与每种电线类型相关联; 确定穿过所述第一电路元件和所述第二电路元件之间的路由网格的所有可能路径; 确定每个路径的加权长度; 并选择具有最低加权长度的路径。

公开(公告)号：US07755408B2

公开(公告)日：2010-07-13

申请号：US11868637

申请日：2007-10-08

申请人： Sebastian Ehrenreich ,  Juergen Koehl ,  Juergen Pille

发明人： Sebastian Ehrenreich ,  Juergen Koehl ,  Juergen Pille

IPC分类号： G06F1/04 ,  H03K1/04

CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/007

摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.

摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /我们以前的子树。

公开(公告)号：US07392497B2

公开(公告)日：2008-06-24

申请号：US11160607

申请日：2005-06-30

申请人： Uwe Fassnacht ,  Juergen Koehl

发明人： Uwe Fassnacht ,  Juergen Koehl

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.

摘要翻译： 一种布置集成电路的互连金属层的方法，其中单宽网络被复制并并行布线以减少网上的总电阻; 宽电线分解成并行布线的几根单宽线，以提高金属互连线路的均匀性，从而提高金属互连层的可制造性。 在初始物理放置之后的初步线路中执行分解步骤。 通过并行单宽度导线的分支和复合来确保对销形状的访问。 单独的线段在网的源和汇处重新连接。 并联线段不会改变电路的逻辑特性。

公开(公告)号：US20080059933A1

公开(公告)日：2008-03-06

申请号：US11845892

申请日：2007-08-28

申请人： Erich Barke ,  Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

发明人： Erich Barke ,  Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

IPC分类号： G06F17/50

CPC分类号： G06F17/509 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/78 ,  G06F2217/84

摘要： The present invention relates to a method for designing fan-out nets connecting a signal source and a plurality of net elements in an integrated circuit. In order to make fan-out nets more robust against opens while keeping the risk due to short circuits in an acceptable degree, the method comprises the steps of: a) implementing a routing section in a closed structure comprising a plurality of signal receiving pins, wherein said receiving pins connect to further net elements, b) implementing on said closed structure a plurality of buffer elements to provide multiple signals derived from said source signal for driving said plurality of net elements, and c) limiting the distance and number of receiving cells between two buffer elements below predetermined values in order to keep a short circuit current given in case of an open tolerably small and within a worst case skew time delay.

摘要翻译： 本发明涉及一种在集成电路中设计连接信号源和多个网元的扇出网络的方法。 为了使扇出网络在打开的同时保持较强的鲁棒性，同时将短路的风险保持在可接受的程度，该方法包括以下步骤：a）实现包括多个信号接收引脚的封闭结构中的路由部分， 其中所述接收引脚连接到另外的网元件，b）在所述封闭结构上实现多个缓冲元件以提供从所述源信号导出的多个信号，用于驱动所述多个网元，以及c）限制接收单元的距离和数量 在两个缓冲元件之间低于预定值，以便在开路容许小的情况下以及在最坏情况下的扭曲时间延迟中保持短路电流。

公开(公告)号：US20070240085A1

公开(公告)日：2007-10-11

申请号：US11279300

申请日：2006-04-11

申请人： Jeanne Bickford ,  Jason Hibbeler ,  Juergen Koehl

发明人： Jeanne Bickford ,  Jason Hibbeler ,  Juergen Koehl

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5081

摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

摘要翻译： 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预先扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时预结构。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。

公开(公告)号：US07206308B2

公开(公告)日：2007-04-17

申请号：US10290645

申请日：2002-11-08

申请人： Juergen Koehl ,  Ronald Peter Luijten

发明人： Juergen Koehl ,  Ronald Peter Luijten

IPC分类号： H04Q11/00

CPC分类号： H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13166 ,  H04Q2213/1334 ,  H04Q2213/13341

摘要： Method and apparatus for providing a non-blocking routing network for establishing arbitrary connections between n primary nodes (m—0, . . . , m_n−1) and N≧n secondary nodes (r—0, . . . , r_N−1). The routing network requires less physical connections than a corresponding Clos routing network while having small transmission delays. One embodiment of the invention provides a routing network that is well suited for direct on-chip implementation due to the matrix structure of the routing network.

摘要翻译： 用于提供非阻塞路由网络的方法和装置，用于建立n个主节点（m-1，...，m-n-1）之间的任意连接以及N个= n个次节点（r < SUB，-0，...，rNN-1）。 路由网络需要比对应的Clos路由网络更少的物理连接，同时具有较小的传输延迟。 本发明的一个实施例提供了一种由于路由网络的矩阵结构而非常适合于直接片上实现的路由网络。

公开(公告)号：US20120144362A1

公开(公告)日：2012-06-07

申请号：US13311651

申请日：2011-12-06

申请人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

发明人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

摘要： A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.

摘要翻译： 公开了一种优化电路设计性能的方法。 该方法包括为电路的每个电路元件设计可用的设计参数选项; 将电路设计和设计参数选项转换为线性规划模型; 确定线性规划模型的解决方案; 并且基于产生电路元件列表的解决方案，其中设计参数需要改变为不同的选项以实现性能优化。

公开(公告)号：US20110289468A1

公开(公告)日：2011-11-24

申请号：US12949998

申请日：2010-11-19

申请人： Joachim Keinert ,  Juergen Koehl ,  Thomas Ludwig

发明人： Joachim Keinert ,  Juergen Koehl ,  Thomas Ludwig

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).

摘要翻译： 通过基于由宏端口权重值，宏端口排序中的任何一个组成的标准修改可修改的轮廓形状宏的轮廓来操纵电子电路设计的固定轮廓形状和可修改轮廓形状的随机逻辑宏。 宏观融合约束或宏观逻辑深度，并将结果宏放置在集成电路（芯片）的位置。