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    Methods and apparatus for processing variable length coded data
    41.
    发明授权
    Methods and apparatus for processing variable length coded data 失效
    用于处理可变长度编码数据的方法和装置

    公开(公告)号：US07804430B2

    公开(公告)日：2010-09-28

    申请号：US12133489

    申请日：2008-06-05

    申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

    发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

    IPC分类号： H03M7/40

    CPC分类号： H03M7/40

    摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

    摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

    IMAGE PROCESSING METHODS AND SYSTEMS FOR FRAME RATE CONVERSION
    42.
    发明申请
    IMAGE PROCESSING METHODS AND SYSTEMS FOR FRAME RATE CONVERSION 有权
    图像处理方法和帧速率转换系统

    公开(公告)号：US20090273710A1

    公开(公告)日：2009-11-05

    申请号：US12433686

    申请日：2009-04-30

    申请人： Larry Pearlstein ,  Samir Hulyalkar

    发明人： Larry Pearlstein ,  Samir Hulyalkar

    IPC分类号： H04N7/01

    CPC分类号： G06T3/4007 ,  G09G5/006 ,  G09G2340/0435 ,  H04N7/0132 ,  H04N7/0135

    摘要： An image processing method for frame rate conversion, comprising: receiving a stream of input pictures at an input frame rate, at least some of the input pictures being new pictures, the new pictures appearing within the stream of input pictures at an underlying new picture rate; generating interpolated pictures from certain ones of the input pictures; outputting a stream of output pictures at an output frame rate, the stream of output pictures including a blend of the new pictures and the interpolated pictures, the interpolated pictures appearing in the stream of output pictures at an average interpolated picture rate; and causing a variation in the average interpolated picture rate in response to detection of a variation in the underlying new picture rate.

    摘要翻译： 一种用于帧速率转换的图像处理方法，包括：以输入帧速率接收输入图像流，所述输入图像中的至少一些是新图像，所述新图像以基本新图像速率出现在所述输入图像流内 ; 从某些输入图像生成内插图像; 以输出帧速率输出输出图像流，输出图像流包括新图像和内插图像的混合，内插图像以平均内插图像速率出现在输出图像流中; 并且响应于底层新图像速率的变化的检测而导致平均内插图像速率的变化。

    SYSTEMS, METHODS, AND APPARATUS FOR SYNCHRONIZATION OF AUDIO AND VIDEO SIGNALS
    43.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR SYNCHRONIZATION OF AUDIO AND VIDEO SIGNALS 有权
    用于音频和视频信号同步的系统，方法和装置

    公开(公告)号：US20070276670A1

    公开(公告)日：2007-11-29

    申请号：US11754096

    申请日：2007-05-25

    申请人： Larry Pearlstein

    发明人： Larry Pearlstein

    IPC分类号： G10L21/00

    CPC分类号： H04N21/2368 ,  G10L19/167 ,  H04N21/4307 ,  H04N21/4341 ,  H04N21/44004

    摘要： Methods of processing an audiovisual signal that has a video portion and an audio portion are described. One example includes detecting a video synchronization event in the video portion and, in response to the detecting, embedding a marker relating to the video synchronization event into a serial data stream carrying the audio portion. The serial data stream includes a series of packets, each packet having (A) a preamble that includes a synchronization sequence, (B) an auxiliary data field, and (C) a main data field.

    摘要翻译： 描述处理具有视频部分和音频部分的视听信号的方法。 一个示例包括检测视频部分中的视频同步事件，并且响应于检测将与视频同步事件有关的标记嵌入到携带音频部分的串行数据流中。 串行数据流包括一系列分组，每个分组具有（A）包括同步序列的前同步码，（B）辅助数据字段和（C）主数据字段。

    SIMD processor executing min/max instructions
    45.
    发明申请
    SIMD processor executing min/max instructions 有权

    公开(公告)号：US20060095739A1

    公开(公告)日：2006-05-04

    申请号：US10940123

    申请日：2004-09-13

    申请人： Richard Selvaggi ,  Larry Pearlstein

    发明人： Richard Selvaggi ,  Larry Pearlstein

    IPC分类号： G06F9/44

    CPC分类号： G06F9/30036 ,  G06F9/30021

    摘要： A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

    Methods and apparatus for processing variable length coded data
    46.
    发明申请
    Methods and apparatus for processing variable length coded data 有权

    公开(公告)号：US20060071829A1

    公开(公告)日：2006-04-06

    申请号：US11046048

    申请日：2005-01-28

    申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

    发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

    IPC分类号： H03M7/40

    CPC分类号： H03M7/40

    摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

    Methods and apparatus for representing different portions of an image at different resolutions
    47.
    发明授权
    Methods and apparatus for representing different portions of an image at different resolutions 失效

    公开(公告)号：US06668018B2

    公开(公告)日：2003-12-23

    申请号：US10090860

    申请日：2002-03-05

    申请人： Larry Pearlstein ,  John Henderson ,  Jack Fuhrer

    发明人： Larry Pearlstein ,  John Henderson ,  Jack Fuhrer

    IPC分类号： H04N736

    CPC分类号： H04N19/30 ,  H04N19/51

    摘要： Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. One specific embodiment is directed to a new video decoder which decodes portions of a single image, e.g., frame, at different resolutions. Areas of the image along high contrast vertical or horizontal edges are decoded at full resolution while other portions of the same image are decoded at reduced resolution. By decoding and storing portions of reduced resolution images at full resolution for reference purposes, the risk of prediction errors resulting from the use of downsampling on reference frames is reduced.

    Registers and methods for accessing registers for use in a single instruction multiple data system
    49.
    发明授权
    Registers and methods for accessing registers for use in a single instruction multiple data system 失效
    访问寄存器的寄存器和方法用于单指令多数据系统

    公开(公告)号：US06175892B1

    公开(公告)日：2001-01-16

    申请号：US09099989

    申请日：1998-06-19

    申请人： Sharif Mohammad Sazzad ,  Larry Pearlstein

    发明人： Sharif Mohammad Sazzad ,  Larry Pearlstein

    IPC分类号： G06F1200

    CPC分类号： G06F9/30032 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30141 ,  G11C7/1006

    摘要： Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.

    摘要翻译： 描述了实现单指令多数据（SIMD）信号处理操作的方法和装置。 本发明的装置包括新的寄存器和寄存器阵列，其允许以字以及子字或子寄存器级别访问数据。 当基于SIMD架构实现系统时，可以使用本发明的寄存器和寄存器阵列。 根据本发明实现的寄存器包括多个通过门，其允许存储在寄存器中的整个n位字被访问并输出为单个字或要存储的字的子字部分被访问， 输出。 在标准操作期间，寄存器是以字为单位访问的。 然而，在列访问操作期间，例如，当执行转置操作时，以子字为基础执行访问。 在字或子字级别访问本发明的寄存器的能力使得实现转置和各种其他行/列数据操纵操作可以以相对直接的方式进行，而不需要数据缓冲。 除了本发明的新型寄存器和寄存器阵列之外，本发明的各个方面涉及新的和新颖的SIMD指令，例如SIMD移动，添加和移动指令，其支持要处理的数据的规范为 识别寄存器阵列的行或列的操作数，而不是像传统命令一样完成标识寄存器。 还支持转置命令。

    Methods and apparatus for reducing the cost of video decoders
    50.
    发明授权
    Methods and apparatus for reducing the cost of video decoders 失效
    降低视频解码器成本的方法和设备

    公开(公告)号：US6148032A

    公开(公告)日：2000-11-14

    申请号：US105223

    申请日：1998-06-26

    申请人： Larry Pearlstein ,  Sharif M. Sazzad

    发明人： Larry Pearlstein ,  Sharif M. Sazzad

    IPC分类号： H04N7/32 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/12

    CPC分类号： H04N19/00 ,  H04N19/17 ,  H04N19/186 ,  H04N19/423 ,  H04N19/45 ,  H04N19/60 ,  H04N19/61 ,  H04N19/30 ,  H04N19/70

    摘要： Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques. The decoded I and P frame data is stored for use when making subsequent predictions if required. Another data reduction technique involves applying different amounts of data reduction, e.g., downsampling, to different image portions with no or little downsampling being performed on image portions located at or nearest to the image's center of interest as determined from information included in a received encoded bitstream.

    摘要翻译： 描述了以降低的成本实现视频解码器的方法和装置。 该方法包括数据简化技术，简化逆量化技术，以及动态地改变图像增强操作的复杂性，例如预测滤波操作，作为是否正在处理亮度或色度数据的函数。 为了减少数据存储要求，与以前编码的图像相对应的亮度和色度数据可以以不同的分辨率存储，在一些实施例中，色度数据被存储在亮度数据的分辨率的一半以下。 在各种实施例中，表示不显示的B帧的部分的数据被识别和丢弃，例如不对其执行解码操作。 以降低的分辨率和/或使用简化的逆量化技术来识别和解码不显示的I帧和P帧的部分。 如果需要，进行后续预测时，解码的I和P帧数据被存储以供使用。 另一种数据缩减技术涉及对不同的图像部分应用不同数量的数据缩减，例如下采样，在从包含在接收的编码比特流中的信息确定的位于或最靠近图像的感兴趣中心的图像部分上执行没有或很少的下采样 。