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73 条记录 (耗时 0.028 秒)

    VERTICAL NAND DEVICE WITH LOW CAPACITANCE AND SILICIDED WORD LINES
    41.
    发明申请
    VERTICAL NAND DEVICE WITH LOW CAPACITANCE AND SILICIDED WORD LINES 有权
    具有低电容和无水字线的垂直NAND器件

    公开(公告)号：US20130264631A1

    公开(公告)日：2013-10-10

    申请号：US13443287

    申请日：2012-04-10

    申请人： Johann Alsmeier ,  Peter Rabkin

    发明人： Johann Alsmeier ,  Peter Rabkin

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/1157 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/7926

    摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.

    摘要翻译： 一种包括衬底和半导体沟道的三维存储器件。 半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。 该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。 多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于第二器件电平的第二控制栅电极。 多个控制栅电极中的每一个包括基本上不含硅化物的第一边缘表面，面向半导体沟道的第一边缘表面和至少一个电荷存储区域以及位于控制栅电极的剩余表面上的硅化物。

    Selective Word Line Erase In 3D Non-Volatile Memory
    43.
    发明申请
    Selective Word Line Erase In 3D Non-Volatile Memory 有权

    公开(公告)号：US20130107628A1

    公开(公告)日：2013-05-02

    申请号：US13287343

    申请日：2011-11-02

    申请人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

    发明人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

    IPC分类号： G11C16/16

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11582 ,  H01L29/7926

    摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

    STACKED METAL FIN CELL
    45.
    发明申请
    STACKED METAL FIN CELL 有权
    堆积金属细胞

    公开(公告)号：US20120153376A1

    公开(公告)日：2012-06-21

    申请号：US12974235

    申请日：2010-12-21

    申请人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

    发明人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

    摘要： A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.

    摘要翻译： 一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。 多个导电翅片中的每一个位于多个浮动栅极之一上。 多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。 多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

    ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF
    46.
    发明申请
    ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权

    公开(公告)号：US20120001250A1

    公开(公告)日：2012-01-05

    申请号：US12827869

    申请日：2010-06-30

    申请人： Johann Alsmeier

    发明人： Johann Alsmeier

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7889 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7926

    摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

    Method for fabricating a semiconductor structure
    49.
    发明授权
    Method for fabricating a semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US07259060B2

    公开(公告)日：2007-08-21

    申请号：US10995677

    申请日：2004-11-23

    申请人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

    发明人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

    摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

    摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。