公开(公告)号：US06876022B2

公开(公告)日：2005-04-05

申请号：US10306592

申请日：2002-11-27

申请人： Craig T. Salling ,  Brian W. Huber

发明人： Craig T. Salling ,  Brian W. Huber

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391

摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

公开(公告)号：US06741121B2

公开(公告)日：2004-05-25

申请号：US10228704

申请日：2002-08-27

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G06G712

CPC分类号： H03F3/45695

摘要： An amplifying circuit includes a compensation unit with a feeding forward path to reduce the effect of the common mode noise on the output signals of a differential amplifier. The compensation unit includes a capacitive network connected to input nodes and output nodes of the differential amplifier. The capacitive network provides the feeding forward path.

摘要翻译： 放大电路包括具有馈送路径的补偿单元，以减小共模噪声对差分放大器的输出信号的影响。 补偿单元包括连接到差分放大器的输入节点和输出节点的电容网络。 电容网络提供馈送路径。

公开(公告)号：US06693485B1

公开(公告)日：2004-02-17

申请号：US10231920

申请日：2002-08-29

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G06G712

CPC分类号： H03F3/45708 ,  H03F3/4565 ,  H03F2203/45362 ,  H03F2203/45401 ,  H03F2203/45418 ,  H03F2203/45426 ,  H03F2203/45466

摘要： An amplifying circuit includes a differential amplifier for receiving input signals to generate output signals. A current regulator unit and an input enhancement unit allow the input signals to exceed the normal input range of the differential amplifier. The current regulator unit regulates current in the differential amplifier. The input enhancement unit steers current from a first current path to a second current path based on signal levels of the input signals.

摘要翻译： 放大电路包括用于接收输入信号以产生输出信号的差分放大器。 电流调节器单元和输入增强单元允许输入信号超过差分放大器的正常输入范围。 电流调节器单元调节差分放大器中的电流。 输入增强单元基于输入信号的信号电平将电流从第一电流路径转移到第二电流路径。

公开(公告)号：US06434061B1

公开(公告)日：2002-08-13

申请号：US09654098

申请日：2000-08-31

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/22

摘要： A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

公开(公告)号：US06433593B1

公开(公告)日：2002-08-13

申请号：US09977661

申请日：2001-10-15

申请人： Brian W. Huber ,  David Lisenbe

发明人： Brian W. Huber ,  David Lisenbe

IPC分类号： H03F300

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  H03K17/163

摘要： A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

摘要翻译： 一种用于支持输出驱动器电路中的电压并平滑电压对输出驱动器电路中的开关操作的响应的方法和装置。 诸如电容器或晶体管的电容元件耦合到输出驱动器的输出驱动器支路电路中的驱动晶体管的栅极和开关信号电压。 通过将电容元件耦合到除地之外的信号电压，需要比将电容元件耦合到地所需要的电容元件更小的电容元件。 本发明的实施例还包括多个电容元件，其被配置为使得电压支持被相位而不是全部施加到驱动晶体管的栅极，以平滑电压响应以驱动晶体管切换。 具有相对较长有效沟道长度的晶体管可以用作电容元件，以允许由于通过较长沟道的信号延迟而导致的电压支持的附加定相。

公开(公告)号：US06411562B1

公开(公告)日：2002-06-25

申请号：US09792537

申请日：2001-02-23

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G11C800

CPC分类号： G11C5/147 ,  G11C5/145

摘要： The present invention relates generally to a method and apparatus of producing a control pulse of an extended duration for use in a voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator.

摘要翻译： 本发明一般涉及一种用于电压调节器中产生延长持续时间的控制脉冲的方法和装置。 第一逻辑门接收多个信号，每个信号代表多个输出块之一的电压需求，并产生第一持续时间的控制脉冲。 多个延迟电路接收控制脉冲并产生多个延迟的控制脉冲。 第二逻辑门接收控制脉冲和多个延迟的控制脉冲，并产生延长的持续时间的控制脉冲。 可以使用延长持续时间的控制脉冲，例如用于临时将附加电流提供给电压调节器的输出端子。

公开(公告)号：US06259646B1

公开(公告)日：2001-07-10

申请号：US09493452

申请日：2000-01-28

申请人： Brian W. Huber

发明人： Brian W. Huber

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C7/1018 ,  G11C8/04

摘要： Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circuitry coupled to the decode logic circuitry that generates a counter value based on the decoded address. Other embodiments of a structure include a compare circuit that determines whether a page count is complete in a memory structure. The compare circuit includes a holding circuitry that includes a number of latches for holding an encoded version of a memory address. The compare circuit also includes a multiplexing circuitry coupled to the holding circuitry. The multiplexing circuitry receives the encoded version of the memory address from the holding circuitry and a decoded version of the memory address from a decoder, such that the multiplexing circuitry uses the encoded version to select one bit of the decoded version of the memory address to determine whether the page count is complete for the memory structure. Embodiments of the present invention also includes methods, other structures as well as systems incorporating such structures all formed according to the methods provided in this application.

摘要翻译： 提供了改进的方法和结构，其允许快速访问存储器设备。 结构的实施例包括存储器件，其包括解码地址的解码逻辑电路。 存储器件还包括耦合到解码逻辑电路的计数器电路，其基于解码的地址生成计数器值。 结构的其他实施例包括确定存储器结构中页数是否完成的比较电路。 比较电路包括保持电路，该保持电路包括用于保持存储器地址的编码版本的多个锁存器。 比较电路还包括耦合到保持电路的复用电路。 多路复用电路从保持电路接收存储器地址的编码版本和来自解码器的存储器地址的解码版本，使得复用电路使用编码版本来选择存储器地址的解码版本的一个位以确定 内存结构的页数是否完整。 本发明的实施例还包括方法，其他结构以及结合这种结构的系统，其全部根据本申请中提供的方法形成。

公开(公告)号：US06191995B1

公开(公告)日：2001-02-20

申请号：US09386101

申请日：1999-08-30

申请人： Brian W. Huber ,  Todd A. Dauenbaugh

发明人： Brian W. Huber ,  Todd A. Dauenbaugh

IPC分类号： G11C1300

CPC分类号： G11C5/025 ,  G11C5/063

摘要： A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.

摘要翻译： 存储器件包括存储器阵列和至少两组行解码器以驱动存储器阵列中的行线。 选择行（例如行选择行）携带信号以在两组解码器之一中选择一个或多个解码器。 至少一些选择线在两组行解码器之间共享，以减少在存储器阵列中路由信号线所需的空间。

公开(公告)号：US6052307A

公开(公告)日：2000-04-18

申请号：US368053

申请日：1999-08-03

申请人： Brian W. Huber ,  Theodore T. Pekny

发明人： Brian W. Huber ,  Theodore T. Pekny

IPC分类号： G11C7/14 ,  G11C16/26 ,  G11C16/06

CPC分类号： G11C7/14 ,  G11C16/26

摘要： A leakage tolerant sense circuit for use in an electrically programmable and erasable read only memory (EEPROM) is disclosed. In a reference portion of a sense cycle, the leakage tolerant sense amplifier utilizes the sum of a reference current and any leakage current to establish a reference voltage. In the subsequent sense portion of the sense cycle, the leakage tolerant sense amplifier utilizes the sum of a memory cell current and any leakage current to establish a read voltage. The read voltage is compared with the reference voltage to determine the logic stored within the memory cell.

摘要翻译： 公开了一种用于电可编程和可擦除只读存储器（EEPROM）的漏电容量检测电路。 在感测周期的参考部分中，泄漏容忍读出放大器利用参考电流和任何漏电流的和建立参考电压。 在感测周期的后续感测部分中，泄漏容忍读出放大器利用存储单元电流和任何泄漏电流的和建立读取电压。 将读取电压与参考电压进行比较，以确定存储单元内存储的逻辑。