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    MEMORY SYSTEM CHANGING WRITE SIZE AND WRITE MODE AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CHANGING WRITE SIZE AND WRITE MODE
    41.
    发明申请
    MEMORY SYSTEM CHANGING WRITE SIZE AND WRITE MODE AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CHANGING WRITE SIZE AND WRITE MODE 有权

    公开(公告)号：US20250060894A1

    公开(公告)日：2025-02-20

    申请号：US18938394

    申请日：2024-11-06

    Applicant: KIOXIA CORPORATION

    Inventor： Shinichi KANNO

    IPC: G06F3/06 ,  G11C8/08

    Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.

    MEMORY SYSTEM
    44.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240086099A1

    公开(公告)日：2024-03-14

    申请号：US18516632

    申请日：2023-11-21

    Applicant: Kioxia Corporation

    Inventor： Naoki ESAKA ,  Shinichi KANNO

    IPC: G06F3/06

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

    MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    45.
    发明公开
    MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20240086096A1

    公开(公告)日：2024-03-14

    申请号：US18509572

    申请日：2023-11-15

    Applicant: KIOXIA CORPORATION

    Inventor： Yuki SASAKI ,  Shinichi KANNO

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0292

    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    46.
    发明公开
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20240070006A1

    公开(公告)日：2024-02-29

    申请号：US18180234

    申请日：2023-03-08

    Applicant: Kioxia Corporation

    Inventor： Shinichi KANNO ,  Yuki SASAKI

    IPC: G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/0772 ,  G06F11/076 ,  G06F11/1489

    Abstract: According to one embodiment, when a code rate is less than 1, a controller encodes a plurality of pieces of write data to generate a codeword including the plurality of pieces of write data and one or more erasure recovery codes. The controller calculates a cumulative error count. The controller calculates at least one of a cumulative write amount or a cumulative read amount. The controller change the code rate such that the code rate is increased when a first value which is obtained by dividing the cumulative error count by the cumulative write amount or the cumulative read amount is less than a first threshold value, and the code rate is decreased when the first value is larger than or equal to a second threshold value.

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    47.
    发明公开
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20230367501A1

    公开(公告)日：2023-11-16

    申请号：US18357231

    申请日：2023-07-24

    Applicant: KIOXIA CORPORATION

    Inventor： Shinichi KANNO

    IPC: G06F3/06 ,  G11C8/08

    CPC classification number: G06F3/064 ,  G06F3/0656 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0652 ,  G11C8/08 ,  G06F3/0679

    Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.

    SYSTEM AND METHOD OF WRITING TO NONVOLATILE MEMORY USING WRITE BUFFERS
    48.
    发明公开
    SYSTEM AND METHOD OF WRITING TO NONVOLATILE MEMORY USING WRITE BUFFERS 审中-公开

    公开(公告)号：US20230325112A1

    公开(公告)日：2023-10-12

    申请号：US18333962

    申请日：2023-06-13

    Applicant: KIOXIA CORPORATION

    Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0679 ,  G06F3/0604 ,  G06F12/0804

    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

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