公开(公告)号：US20070221955A1

公开(公告)日：2007-09-27

申请号：US11724389

申请日：2007-03-15

申请人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami ,  Masakatsu Hoshi

发明人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami ,  Masakatsu Hoshi

IPC分类号： H01L29/739

CPC分类号： H01L29/7828 ,  H01L21/0273 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66068

摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.

摘要翻译： 形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。 此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。

公开(公告)号：US20070181886A1

公开(公告)日：2007-08-09

申请号：US11701429

申请日：2007-02-02

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L31/0312

CPC分类号： H01L29/267 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.

摘要翻译： 一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域 导电性半导体基板彼此接触，从而形成三重接触点。 第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。

公开(公告)号：US08786011B2

公开(公告)日：2014-07-22

申请号：US13643468

申请日：2011-04-27

申请人： Shigeharu Yamagami ,  Tetsuya Hayashi ,  Tatsuhiro Suzuki

发明人： Shigeharu Yamagami ,  Tetsuya Hayashi ,  Tatsuhiro Suzuki

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/82 ,  H01L27/07 ,  H01L29/861 ,  H01L29/872 ,  H01L29/16 ,  H01L21/04 ,  H01L29/20

CPC分类号： H01L21/8213 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/823487 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.

摘要翻译： 每个绝缘栅极部分在位于漂移区域和源极区域之间的第一阱区域的一部分中形成沟道。 第一主电极与漂移区的主表面露出的部分漂移区形成结，以构成单极二极管并连接到第一阱区和源极区。 当从主表面的法线方向观察时，多个绝缘栅极部分具有彼此平行的线状图案。 在每对相邻的绝缘栅极部分之间，沿着绝缘栅极部分延伸的方向布置有第一主电极与漂移区域连接的接合部分和第一阱区域。 通道至少沿主表面的法线方向形成。

公开(公告)号：US20130043524A1

公开(公告)日：2013-02-21

申请号：US13643468

申请日：2011-03-27

申请人： Shigeharu Yamagami ,  Tetsuya Hayashi ,  Tatsuhiro Suzuki

发明人： Shigeharu Yamagami ,  Tetsuya Hayashi ,  Tatsuhiro Suzuki

IPC分类号： H01L29/78

CPC分类号： H01L21/8213 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/823487 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.

摘要翻译： 每个绝缘栅极部分在位于漂移区域和源极区域之间的第一阱区域的一部分中形成沟道。 第一主电极与漂移区的主表面露出的部分漂移区形成结，以构成单极二极管并连接到第一阱区和源极区。 当从主表面的法线方向观察时，多个绝缘栅极部分具有彼此平行的线状图案。 在每对相邻的绝缘栅极部分之间，沿着绝缘栅极部分延伸的方向布置有第一主电极与漂移区域连接的接合部分和第一阱区域。 通道至少沿主表面的法线方向形成。

公开(公告)号：US08067776B2

公开(公告)日：2011-11-29

申请号：US12105318

申请日：2008-04-18

申请人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

发明人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

IPC分类号： H01L29/12 ,  H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66068 ,  H01L29/513 ,  H01L29/7828

摘要： Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.

摘要翻译： 本文教导了制造包括半导体衬底和包括具有与半导体衬底的带隙不同的带隙并与半导体衬底的第一表面的一部分接触的半导体材料的半导体区域的半导体器件的制造方法， 设备。 该方法包括在半导体衬底的第一表面的暴露部分和异质半导体材料的暴露表面上沉积第一绝缘膜，并在第一绝缘膜和半导体衬底和异质半导体的相对表面之间形成第二绝缘膜 通过在氧化气氛中进行热处理。

公开(公告)号：US07989295B2

公开(公告)日：2011-08-02

申请号：US13014190

申请日：2011-01-26

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L21/336

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068

摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.

公开(公告)号：US07902555B2

公开(公告)日：2011-03-08

申请号：US12325377

申请日：2008-12-01

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7828

摘要： A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.

摘要翻译： 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。

公开(公告)号：US07671383B2

公开(公告)日：2010-03-02

申请号：US11714214

申请日：2007-03-06

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/732

CPC分类号： H01L29/267 ,  H01L21/0475 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

摘要翻译： 一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线 接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

公开(公告)号：US20090278169A1

公开(公告)日：2009-11-12

申请号：US12065847

申请日：2006-08-22

申请人： Tetsuya Hayashi ,  Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L21/046 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.

摘要翻译： 半导体器件包括：半导体基底; 与半导体基底接触并且具有与半导体基底不同的带隙的异质半导体区域; 连接到所述异质半导体区域的第一电极; 以及形成与半导体基底的欧姆接触的第二电极。 异质半导体区域包括通过层叠在至少两层之间的边界处晶体取向不连续的多个半导体层而形成的层叠异质半导体区域。

公开(公告)号：US20080303036A1

公开(公告)日：2008-12-11

申请号：US12105318

申请日：2008-04-18

申请人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

发明人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

IPC分类号： H01L29/15 ,  H01L21/00

CPC分类号： H01L29/66068 ,  H01L29/513 ,  H01L29/7828

摘要： Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.

摘要翻译： 本文教导了制造包括半导体衬底和包括具有与半导体衬底的带隙不同的带隙并与半导体衬底的第一表面的一部分接触的半导体材料的半导体区域的半导体器件的制造方法， 设备。 该方法包括在半导体衬底的第一表面的暴露部分和异质半导体材料的暴露表面上沉积第一绝缘膜，并在第一绝缘膜和半导体衬底和异质半导体的相对表面之间形成第二绝缘膜 通过在氧化气氛中进行热处理。