SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND PATTERNING MASK UTILIZIED BY THE METHOD
    41.
    发明申请
    SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND PATTERNING MASK UTILIZIED BY THE METHOD 有权
    半导体器件,其制造方法以及由该方法使用的掩模图案

    公开(公告)号:US20120061737A1

    公开(公告)日:2012-03-15

    申请号:US13301657

    申请日:2011-11-21

    摘要: A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

    摘要翻译: 半导体器件。 该器件包括由衬底上的隔离结构隔离的有源区。 该器件还包括延伸跨过有源区并覆盖衬底的栅电极,一对源极区和漏极区,设置在有源区中的衬底上的栅电极的任一侧上,栅电介质层位于 基板和栅电极。 栅介质层包括相对较厚的高电压(HV)电介质部分和相对较薄的低电压(LV)电介质部分,其中HV电介质部分占据漏区,隔离结构和栅极之间的第一交点 电极,以及源区域,隔离结构和栅电极之间的第二交叉点。

    Synchronization channel for advanced wireless OFDM/OFDMA systems
    43.
    发明申请
    Synchronization channel for advanced wireless OFDM/OFDMA systems 有权
    高级无线OFDM / OFDMA系统的同步信道

    公开(公告)号:US20100165942A1

    公开(公告)日:2010-07-01

    申请号:US12655515

    申请日:2009-12-30

    IPC分类号: H04W88/16 H04W72/04 H04L27/28

    摘要: A hierarchical downlink (DL) synchronization channel (SCH) is provided for wireless OFDM/OFDMA systems. The SCH includes a Primary SCH (P-SCH) for carrying PA-Preambles used for coarse timing and frequency synchronization, and a Secondary SCH (S-SCH) for carrying SA-Preambles used for cell ID detection. The total time length occupied by P-SCH and S-SCH is equal to one OFDM symbol time length of a data channel, and S-SCH is located in front of P-SCH in each DL frame. A perfect multi-period time-domain structure is created and maintained in P-SCH to increase preciseness of frame boundary estimation. With overlapping deployment of macrocells and femtocells, a predefined SCH configuration scheme is provided to separate frequency subbands used for macrocells and femtocells such that interferences in S-SCH can be mitigated. In addition, a self-organized SCH configuration scheme is provided to allow more flexibility for femtocells to avoid or introduce interference in S-SCH.

    摘要翻译: 为无线OFDM / OFDMA系统提供分层下行链路(DL)同步信道(SCH)。 SCH包括用于携带用于粗定时和频率同步的PA前导的主SCH(P-SCH)和用于携带用于小区ID检测的SA-前导的辅SCH(S-SCH)。 由P-SCH和S-SCH占用的总时间长度等于数据信道的一个OFDM符号时间长度,并且S-SCH位于每个DL帧中的P-SCH前面。 在P-SCH中创建并保持了完美的多周期时域结构,以增加帧边界估计的精确度。 通过宏单元和毫微微小区的重叠部署,提供预定义的SCH配置方案来分离用于宏小区和毫微微小区的频率子带,从而可以减轻S-SCH中的干扰。 另外,提供了自组织的SCH配置方案,以允许毫微微小区更灵活地避免或引入S-SCH中的干扰。

    Apparatus and method for tracking a sampling clock of multi-carrier communication system
    44.
    发明授权
    Apparatus and method for tracking a sampling clock of multi-carrier communication system 有权
    用于跟踪多载波通信系统的采样时钟的装置和方法

    公开(公告)号:US07623583B2

    公开(公告)日:2009-11-24

    申请号:US11307095

    申请日:2006-01-23

    申请人: Kuo-Ming Wu

    发明人: Kuo-Ming Wu

    IPC分类号: H04K1/10

    CPC分类号: H04L27/2662 H04L27/2675

    摘要: An apparatus and a method for tracking a sampling clock of a multi-carrier communication system are disclosed, the apparatus including a data removal module, a phase estimation module, and a sampling clock offset computation module. The data removal module is for generating a plurality of first and second data removal symbols by removing predetermined transmitted data from a plurality of first and second received symbols, respectively. The phase estimation module for generating a first and a second phase shifts according to correlations of the plurality of first and second data removal symbols. The sampling clock offset computation module for generating a control signal utilized to compensate the sampling clock of a plurality of received symbols according to the first and a second phase shifts.

    摘要翻译: 公开了一种用于跟踪多载波通信系统的采样时钟的装置和方法,该装置包括数据去除模块,相位估计模块和采样时钟偏移计算模块。 数据去除模块用于通过分别从多个第一和第二接收符号中去除预定的发送数据来产生多个第一和第二数据去除符号。 用于根据多个第一和第二数据去除符号的相关性产生第一和第二相位的相位估计模块。 采样时钟偏移计算模块,用于根据第一和第二相移产生用于补偿多个接收符号的采样时钟的控制信号。

    Apparatus and method for tracking sampling clock in multi-carrier communication system
    45.
    发明授权
    Apparatus and method for tracking sampling clock in multi-carrier communication system 有权
    多载波通信系统采样时钟跟踪装置及方法

    公开(公告)号:US07583740B2

    公开(公告)日:2009-09-01

    申请号:US11307096

    申请日:2006-01-23

    IPC分类号: H04K1/10

    摘要: An apparatus and method for tracking a sampling clock are disclosed. The apparatus includes a compensating circuit compensating phases of a first and a second received symbols according to a compensating signal and thereby generating a first and a second compensated symbols; a data removal circuit removing a first predetermined transmitted data from the first compensated symbol, and a second predetermined transmitted data from the second compensated symbol and thereby generating a first and a second data removal symbols; and a computing circuit generating a sampling clock offset according to the first and the second data removal symbols, and adjusting the sampling clock signal according to the sampling clock offset.

    摘要翻译: 公开了一种跟踪采样时钟的装置和方法。 该装置包括补偿电路,根据补偿信号补偿第一和第二接收符号的相位,从而产生第一和第二补偿符号; 从第一补偿符号去除第一预定发送数据的数据去除电路和来自第二补偿符号的第二预定发送数据,从而生成第一和第二数据去除符号; 以及计算电路,根据第一和第二数据去除符号产生采样时钟偏移,并根据采样时钟偏移调整采样时钟信号。

    Integrated Schottky Diode and Power MOSFET
    47.
    发明申请
    Integrated Schottky Diode and Power MOSFET 有权
    集成肖特基二极管和功率MOSFET

    公开(公告)号:US20090020826A1

    公开(公告)日:2009-01-22

    申请号:US11778525

    申请日:2007-07-16

    IPC分类号: H01L29/78

    摘要: A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.

    摘要翻译: 半导体结构包括半导体衬底; 半导体衬底中的第一导电类型的第一阱区; 所述第一阱区域上的含金属层,其中所述含金属层和所述第一阱区形成肖特基势垒; 以及第一阱区中的第一导电类型的第一重掺杂区,其中第一重掺杂区与水分离金属层。

    Robust ESD LDMOS Device
    48.
    发明申请
    Robust ESD LDMOS Device 有权
    强大的ESD LDMOS器件

    公开(公告)号:US20090008710A1

    公开(公告)日:2009-01-08

    申请号:US11773364

    申请日:2007-07-03

    IPC分类号: H01L29/78

    摘要: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

    摘要翻译: 半导体器件包括在半导体衬底上的栅电极,其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域,其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度,并且其中第二宽度基本上小于第一宽度。

    LDMOS device with improved ESD performance
    49.
    发明授权
    LDMOS device with improved ESD performance 有权
    LDMOS器件具有改进的ESD性能

    公开(公告)号:US07420252B2

    公开(公告)日:2008-09-02

    申请号:US11337147

    申请日:2006-01-20

    IPC分类号: H01L23/62

    摘要: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

    摘要翻译: 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域,其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上,所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构,用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200% 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电(ESD)电流的阻抗。

    Semiconductor devices and fabrication methods thereof
    50.
    发明申请
    Semiconductor devices and fabrication methods thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号:US20080191276A1

    公开(公告)日:2008-08-14

    申请号:US11703678

    申请日:2007-02-08

    IPC分类号: H01L29/76 H01L21/336

    摘要: Semiconductor devices and fabrication methods thereof. The semiconductor device includes a semiconductor substrate with a body region of a first doping type. A gate structure is patterned on the semiconductor substrate. A single spacer is formed on a first sidewall of the gate structure. A body region of a first doping type is formed in the semiconductor substrate adjacent to a second sidewall of the gate structure. A source region of a second doping type is formed on the body region and having an edge aligned with the second sidewall of the gate structure. A drain region of the second doping type is formed on the semiconductor substrate and having an edge aligned with an exterior surface of the single sidewall.

    摘要翻译: 半导体器件及其制造方法。 半导体器件包括具有第一掺杂类型的体区的半导体衬底。 在半导体衬底上构图栅极结构。 在栅极结构的第一侧壁上形成单个间隔物。 第一掺杂类型的体区形成在与栅极结构的第二侧壁相邻的半导体衬底中。 第二掺杂类型的源极区域形成在主体区域上并且具有与栅极结构的第二侧壁对准的边缘。 第二掺杂类型的漏极区域形成在半导体衬底上并且具有与单个侧壁的外表面对准的边缘。