公开(公告)号：US20050280506A1

公开(公告)日：2005-12-22

申请号：US11210418

申请日：2005-08-24

申请人： Vadim Lobanov ,  Christopher Diorio ,  Todd Humes ,  Scott Cooper

发明人： Vadim Lobanov ,  Christopher Diorio ,  Todd Humes ,  Scott Cooper

IPC分类号： G06K7/00 ,  G08B13/14 ,  H04Q5/22

CPC分类号： G06K7/0008 ,  G06K7/10019 ,  G06K7/10297

摘要： RFID system components, such as readers and tags, communicate where the reader inventories a population of tags. The tags choose randomly one of a plurality of slots in response to each one of the values communicated by the reader and reply according to their chosen slot. The reader may initiate the inventorying by determining a Q-parameter value from a stored value and communicating the Q-parameter value to the tags. The reader may evaluate replies received from the tags in another plurality of tags, determine a second value from evaluating the second replies, and store the second value for future use.

摘要翻译： 诸如读取器和标签之类的RFID系统组件通信读者清点一批标签的位置。 标签响应于读取器传送的每个值并根据其选择的时隙进行应答，随机选择多个时隙中的一个。 读取器可以通过从存储的值确定Q参数值并将Q参数值传递给标签来启动库存。 读者可以评估从另一多个标签中的标签接收到的答复，从评估第二个回复确定第二个值，并存储第二个值以供将来使用。

公开(公告)号：US20050225436A1

公开(公告)日：2005-10-13

申请号：US10824070

申请日：2004-04-13

申请人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

发明人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

IPC分类号： G06K19/07 ,  H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0726

摘要： According to one aspect of the present invention, there is provided a method of calibrating an oscillator within a radio-frequency identification (RFID) circuit for use in an RFID tag. A first calibration value is stored within a non-volatile memory associated with the RFID circuit. The oscillator is calibrated in accordance with the first calibration value. The storing of the first calibration value is performed responsive to receiving a calibration command and an associated update value at the RFID circuit.

摘要翻译： 根据本发明的一个方面，提供了一种校准用于RFID标签的射频识别（RFID）电路内的振荡器的方法。 第一校准值存储在与RFID电路相关联的非易失性存储器内。 振荡器根据第一个校准值进行校准。 响应于在RFID电路处接收校准命令和相关联的更新值来执行第一校准值的存储。

公开(公告)号：US20050225434A1

公开(公告)日：2005-10-13

申请号：US10824048

申请日：2004-04-13

申请人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

发明人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

IPC分类号： G06K19/07 ,  H04Q5/22

CPC分类号： G06K19/0723

摘要： According to one aspect of the present invention, there is provided a method to generate a demodulator clock signal and a modulator clock signal within an RFID circuit for use within an RFID tag. The demodulator clock signal is generated from a radio-frequency signal received at the RFID tag. A modulator clock signal is generated utilizing a first calibration value, stored within a non-volatile memory associated with the RFID tag.

摘要翻译： 根据本发明的一个方面，提供一种在RFID电路内产生解调器时钟信号和调制器时钟信号以在RFID标签内使用的方法。 解调器时钟信号是从在RFID标签处接收的射频信号产生的。 使用存储在与RFID标签相关联的非易失性存储器内的第一校准值产生调制器时钟信号。

公开(公告)号：US20050219932A1

公开(公告)日：2005-10-06

申请号：US10814866

申请日：2004-03-30

申请人： Christopher Diorio ,  Frederic Bernard ,  Todd Humes ,  Alberto Pesavento

发明人： Christopher Diorio ,  Frederic Bernard ,  Todd Humes ,  Alberto Pesavento

IPC分类号： G11C7/20 ,  G11C14/00 ,  G11C16/04 ,  G11C17/12 ,  G11C16/00

CPC分类号： G11C16/0441 ,  G11C7/20 ,  G11C14/00 ,  G11C16/045

摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

公开(公告)号：US20050219931A1

公开(公告)日：2005-10-06

申请号：US10813907

申请日：2004-03-30

申请人： Christopher Diorio ,  Frederic Bernard ,  Todd Humes ,  Alberto Pesavento

发明人： Christopher Diorio ,  Frederic Bernard ,  Todd Humes ,  Alberto Pesavento

IPC分类号： G11C14/00 ,  G11C16/04 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H03K3/0233 ,  G11C16/00

CPC分类号： G11C16/0441 ,  G11C14/00 ,  G11C16/045 ,  H01L27/105 ,  H01L27/115 ,  H01L29/7883 ,  H03K3/02335

摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

公开(公告)号：US20050140449A1

公开(公告)日：2005-06-30

申请号：US11055958

申请日：2005-02-10

申请人： Christopher Diorio ,  Todd Humes ,  Ronald Oliver ,  William Colleran ,  Scott Cooper

发明人： Christopher Diorio ,  Todd Humes ,  Ronald Oliver ,  William Colleran ,  Scott Cooper

IPC分类号： H03F1/30 ,  H03F3/21 ,  H03F3/16

CPC分类号： H03F3/211 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H03F1/30 ,  H03F1/301 ,  H03F3/16 ,  H03F3/45744 ,  H03F2200/174 ,  H03F2203/45121 ,  H03F2203/45341 ,  H03F2203/45474 ,  H03F2203/45661 ,  H03G1/007

摘要： Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

公开(公告)号：US20050099859A1

公开(公告)日：2005-05-12

申请号：US10914968

申请日：2004-08-09

申请人： Christopher Diorio ,  Todd Humes

发明人： Christopher Diorio ,  Todd Humes

IPC分类号： G11C11/54 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883 ,  H01L29/7885

摘要： Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.

摘要翻译： 通过p沟道MOSFET的沟道到漏极结中的空穴冲击电离驱动的热电子注入为写入浮栅存储器提供了一种新的机制。 各种pFET浮栅结构使用这种机制和电子隧道的组合来实现非易失性模拟存储器，非易失性数字存储器或在线学习。 存储器是非易失性的，因为器件使用电隔离的浮动门来存储电子电荷。 这些器件允许在线学习，因为写入存储器的电子注入和隧道机制可能在正常的器件操作期间发生。 存储器更新和学习是双向的，因为注入和隧道机制分别从浮动栅极添加和去除电子。 因为存储器更新取决于存储的存储器和pFET端子电压，并且由于它们是双向的，所以器件可以实现在线学习功能。

公开(公告)号：US20060223246A1

公开(公告)日：2006-10-05

申请号：US11387515

申请日：2006-03-22

申请人： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

发明人： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

IPC分类号： H01L21/338

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

摘要： A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

摘要翻译： 在传统的CMOS工艺中制造了具有改进的性能和多阱结构的肖特基结二极管器件。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括不同掺杂的材料，例如与第一导电类型相反的第二导电类型。 第二口井设置在第一井内。 含金属材料的区域设置在第二阱中以在含金属材料区域和第二阱之间的界面处形成肖特基结。 在一个实施例中，第二井接触设置在第二井的一部分中。

公开(公告)号：US20060226489A1

公开(公告)日：2006-10-12

申请号：US11095938

申请日：2005-03-30

申请人： Bin Wang ,  Todd Humes

发明人： Bin Wang ,  Todd Humes

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/11521 ,  H01L27/11558

摘要： Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities to enhance retention. A charge adjustment circuit is arranged to inject and remove electrons to and from the shared floating gate determining the output of the logic gate circuit when supply voltage is applied to the logic gate circuit. In another embodiment, four transistors are employed to form another logic circuit such as a NOR gate or a NAND gate.

摘要翻译： 采用保持增强型可编程共享浮栅逻辑电路作为NVM单元。 在一个实施例中，NVM单元由具有共享浮动栅极的双晶体管逻辑门电路形成。 逻辑电路是一个逆变器。 共享浮栅部分或完全掺杂有p型杂质以增强保留性。 电荷调整电路被布置成当向逻辑门电路施加电源电压时，向共享浮置栅极注入和去除电子，以确定逻辑门电路的输出。 在另一个实施例中，采用四个晶体管来形成诸如或非门或与非门的另一个逻辑电路。

公开(公告)号：US20060223247A1

公开(公告)日：2006-10-05

申请号：US11387603

申请日：2006-03-22

申请人： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

发明人： Yanjun Ma ,  Ronald Oliver ,  Todd Humes ,  Jaideep Mavoori

IPC分类号： H01L21/338

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

摘要： A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

摘要翻译： 具有改进性能的肖特基结二极管器件是在常规CMOS工艺中制造的。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括掺杂到与第一导电类型相反的第二导电类型的材料。 含金属材料的区域设置在第一阱之上，以在含金属材料区域和第一阱之间的界面处形成肖特基结。 在一个实施例中，第一井接触设置在第一井的一部分中。 第二阱设置在衬底上，其中第二阱包括掺杂到第一导电类型的材料。 在一个实施例中，第一井和第二井不彼此直接接触。