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78 条记录 (耗时 0.073 秒)

    Flash memory pipelined burst read operation circuit, method, and system
    42.
    发明授权
    Flash memory pipelined burst read operation circuit, method, and system 有权
    闪存流水线突发读操作电路，方法和系统

    公开(公告)号：US07079445B2

    公开(公告)日：2006-07-18

    申请号：US10852841

    申请日：2004-05-24

    申请人： Soo-Hwan Choi ,  Jung-Hoon Park

    发明人： Soo-Hwan Choi ,  Jung-Hoon Park

    IPC分类号： G11C7/00

    CPC分类号： G11C16/26

    摘要： Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher data transfer rates than are possible with prior art burst read flash memory devices. Preferably, the flash memory device supports both non-pipelined and pipelined read operations, with the read mode settable from a memory controller. Other embodiments are described and claimed.

    摘要翻译： 在实施例中包括用于闪存设备和系统的方法和装置。 在示例性系统中，流水线突发读取操作允许设备支持比现有技术的突发读取闪存设备可能的更高的数据传输速率。 优选地，闪存设备支持非流水线和流水线读取操作，读取模式可从存储器控制器设置。 描述和要求保护其他实施例。

    Method of displaying a color image and mobile terminal using the same
    43.
    发明申请
    Method of displaying a color image and mobile terminal using the same 审中-公开
    显示彩色图像的方法和使用其的移动终端

    公开(公告)号：US20060109490A1

    公开(公告)日：2006-05-25

    申请号：US11280454

    申请日：2005-11-17

    申请人： Jung-Hoon Park ,  Seock-Woo Jang

    发明人： Jung-Hoon Park ,  Seock-Woo Jang

    IPC分类号： H04N1/60 ,  G03F3/08

    CPC分类号： G09G5/06 ,  G09G3/3607 ,  G09G2360/144

    摘要： A method of displaying a color image and a mobile terminal using the same are provided. Color image information is displayed using a YUV-based mapping table based on a human color perception characteristic, such that the color image can be represented with a minimum amount of data.

    摘要翻译： 提供了显示彩色图像的方法和使用其的移动终端。 使用基于人类颜色感知特性的基于YUV的映射表来显示彩色图像信息，使得可以以最小量的数据表示彩色图像。

    Method of forming silicidation blocking layer
    45.
    发明授权
    Method of forming silicidation blocking layer 失效
    形成硅化阻挡层的方法

    公开(公告)号：US06861369B2

    公开(公告)日：2005-03-01

    申请号：US10142496

    申请日：2002-05-10

    申请人： Jung-Hoon Park

    发明人： Jung-Hoon Park

    IPC分类号： H01L21/205 ,  H01L21/285 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/302

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/823418 ,  H01L29/4933

    摘要： Disclosed is a method of manufacturing a semiconductor device. First, a silicidation blocking layer is formed on a semiconductor substrate by a plasma enhanced chemical vapor deposition process. Next, the silicidation blocking layer in a region in which a metal silicide contact is to be formed is removed by a wet etching process. Next, after a metal layer is formed on the resultant, the silicon in the region and the metal of the metal layer are reacted to form the metal silicide. Since the silicidation blocking layer consisting of PE-SiON is formed at a low temperature of less than 400 Celsius Degrees, it is possible to prevent diffusion and redistribution of impurities in gate and source/drain regions of a transistor during the deposition of the silicidation blocking layer.

    摘要翻译： 公开了半导体器件的制造方法。 首先，通过等离子体增强化学气相沉积工艺在半导体衬底上形成硅化阻挡层。 接下来，通过湿式蚀刻工艺除去要形成金属硅化物接触的区域中的硅化阻挡层。 接下来，在所得物上形成金属层之后，使该区域中的硅和金属层的金属反应而形成金属硅化物。 由于在低于400摄氏度的低温下形成由PE-SiON组成的硅化阻挡层，所以可以防止在硅化物封闭期间晶体管的栅极和源极/漏极区域中的杂质的扩散和再分布 层。

    Error code pattern generation circuit and semiconductor memory device including the same
    46.
    发明授权
    Error code pattern generation circuit and semiconductor memory device including the same 有权
    误差码图案生成电路和包括其的半导体存储器件

    公开(公告)号：US08612841B2

    公开(公告)日：2013-12-17

    申请号：US12980450

    申请日：2010-12-29

    申请人： Jung-Hoon Park

    发明人： Jung-Hoon Park

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1004 ,  G11C2029/0411

    摘要： An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.

    摘要翻译： 错误码图案生成电路包括被配置为存储错误代码的至少一个位的第一存储单元，以及第一时间段的输出错误数据; 以及第二存储单元，被配置为存储错误代码的至少一个剩余位，并且输出与第一时间段不同的第二时间段的错误数据。

    Semiconductor device
    47.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08476943B2

    公开(公告)日：2013-07-02

    申请号：US12345079

    申请日：2008-12-29

    申请人： Jung-Hoon Park

    发明人： Jung-Hoon Park

    IPC分类号： H04L7/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2254

    摘要： A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.

    摘要翻译： 半导体器件包括：时钟输入单元，被配置为从外部接收系统时钟和数据时钟; 相位分离单元，被配置为响应于系统时钟产生多个多系统时钟，其中每个多系统时钟具有单独的相位差; 相位检测单元，被配置为检测所述多个多系统时钟与所述数据时钟之间的相位差，并响应于所述检测结果产生生成训练信息信号; 以及信号发送单元，被配置为发送训练信息信号。

    Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
    48.
    发明授权
    Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device 有权
    半导体存储器件，包括半导体存储器件的半导体系统以及用于操作半导体存储器件的方法

    公开(公告)号：US08320205B2

    公开(公告)日：2012-11-27

    申请号：US12832815

    申请日：2010-07-08

    申请人： Jung-Hoon Park

    发明人： Jung-Hoon Park

    IPC分类号： G11C7/00

    CPC分类号： G11C7/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    摘要： A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command.

    摘要翻译： 半导体存储器件包括：第一数据输入/输出单元，被配置为响应于训练输入命令接收基于源时钟的边缘扫描其数据窗口的正常训练数据，并且在以下状态下输出数据： 响应于训练输出命令，数据窗口的边缘与源时钟的边沿同步，以及第二数据输入/输出单元，被配置为接收恢复信息训练数据，该数据窗口的数据窗口基于 源时钟，响应于训练输入命令，并且响应于训练输出命令，在数据窗口的边缘与源时钟的边沿同步的状态下输出数据。

    Semiconductor device having auto clock alignment training mode circuit
    49.
    发明授权
    Semiconductor device having auto clock alignment training mode circuit 有权
    具有自动时钟对准训练模式电路的半导体器件

    公开(公告)号：US08115524B2

    公开(公告)日：2012-02-14

    申请号：US12630518

    申请日：2009-12-03

    申请人： Young-Ran Kim ,  Jung-Hoon Park

    发明人： Young-Ran Kim ,  Jung-Hoon Park

    IPC分类号： G11C8/18 ,  H03L7/00

    CPC分类号： G06F1/12 ,  G06F1/06

    摘要： A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result.

    摘要翻译： 一种用于施加自动时钟对准训练模式以减少时钟对准训练操作所需时间的半导体器件。 半导体器件调整自动时钟对准训练模式的进入时间，以防止时钟对准训练操作发生故障。 半导体器件包括：时钟分割块，被配置为分割数据时钟以产生数据分时钟;相位多路复用块，被配置为响应于所述数据分时钟产生多个多个数据分时钟;逻辑电平控制模块，被配置为 根据数据分时钟设定分割控制信号可变的周期，以及第一相位检测块，被配置为基于该周期中的多个数据分时钟来检测系统时钟的相位，并且将第一相位检测块 生成与检测结果对应的分割控制信号。

    SEMICONDUCTOR DEVICE
    50.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110050295A1

    公开(公告)日：2011-03-03

    申请号：US12630518

    申请日：2009-12-03

    申请人： Young-Ran Kim ,  Jung-Hoon Park

    发明人： Young-Ran Kim ,  Jung-Hoon Park

    IPC分类号： H03K21/00

    CPC分类号： G06F1/12 ,  G06F1/06

    摘要： A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result.

    摘要翻译： 一种用于施加自动时钟对准训练模式以减少时钟对准训练操作所需时间的半导体器件。 半导体器件调整自动时钟对准训练模式的进入时间，以防止时钟对准训练操作发生故障。 半导体器件包括：时钟分割块，被配置为分割数据时钟以产生数据分时钟;相位多路复用块，被配置为响应于所述数据分时钟产生多个多个数据分时钟;逻辑电平控制模块，被配置为 根据数据分时钟设定分割控制信号可变的周期，以及第一相位检测块，被配置为基于该周期中的多个数据分时钟来检测系统时钟的相位，并且将第一相位检测块 生成与检测结果对应的分割控制信号。