公开(公告)号：US07659174B2

公开(公告)日：2010-02-09

申请号：US11930230

申请日：2007-10-31

申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

摘要翻译： 在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。 在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。 应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。 在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

公开(公告)号：US07598572B2

公开(公告)日：2009-10-06

申请号：US11552673

申请日：2006-10-25

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Ja-Hum Ku ,  Yong Meng Lee

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Ja-Hum Ku ,  Yong Meng Lee

IPC分类号： H01L29/40

CPC分类号： H01L29/4983 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.

摘要翻译： 一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。 形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。 接触面积由硅化多晶硅间隔物增强。

公开(公告)号：US20080128834A1

公开(公告)日：2008-06-05

申请号：US12014931

申请日：2008-01-16

申请人： Haining Yang ,  Xiangdong Chen ,  Yong Meng Lee ,  Wenhe Lin

发明人： Haining Yang ,  Xiangdong Chen ,  Yong Meng Lee ,  Wenhe Lin

IPC分类号： H01L29/94 ,  H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.

摘要翻译： 公开了减少热载流子劣化的方法和如此形成的半导体结构。 该方法的一个实施例包括在晶体管器件上沉积氮化硅层，将物质离子注入到氮化硅层中以从氮化硅层驱动氢，以及退火以将氢扩散到晶体管器件的沟道区域。 该物质可以选自例如：锗（Ge），砷（As），氙（Xe），氮（N），氧（O），碳（C），硼（B），铟（In） 氩（Ar），氦（He）和氘（De）。 离子注入调节氮化硅层中的原子，例如氢，氮和氢 - 氮键，使得氢可以可控地扩散到沟道区中。

公开(公告)号：US20080102612A1

公开(公告)日：2008-05-01

申请号：US11552673

申请日：2006-10-25

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Ja-Hum Ku ,  Yong Meng Lee

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Ja-Hum Ku ,  Yong Meng Lee

IPC分类号： H01L21/44 ,  H01L21/425 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/4983 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.

摘要翻译： 一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。 形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。 接触面积由硅化多晶硅间隔物增强。

公开(公告)号：US20080090370A1

公开(公告)日：2008-04-17

申请号：US11548870

申请日：2006-10-12

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/32 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

公开(公告)号：US20060014336A1

公开(公告)日：2006-01-19

申请号：US11174857

申请日：2005-07-05

申请人： Yong Meng Lee ,  Da Jin ,  David Vigar

发明人： Yong Meng Lee ,  Da Jin ,  David Vigar

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/7854 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double-gated transistor.

摘要翻译： 形成具有圆形有源区域的双门控晶体管以改善GOI和漏电流控制的方法包括以下步骤。 图案化SOI衬底，并且在图案化的上SOI硅层的暴露侧壁上形成圆形氧化物层。 在暴露的图案化的顶部氧化物层和上部SOI硅层的暴露部分之上形成具有限定栅极的开口的虚设层。 在底切下面的SOI氧化物层中形成底切，去除氧化物层的暴露的栅极区域部分。 去除栅极区域内的圆形氧化物层的部分，并且在该结构的一部分上形成共形氧化物层。 在第二图案化虚拟层开口内形成栅极，去除图案化虚拟层以形成双门控晶体管。

公开(公告)号：US06927104B2

公开(公告)日：2005-08-09

申请号：US10662674

申请日：2003-09-15

申请人： Yong Meng Lee ,  Da Jin ,  David Vigar

发明人： Yong Meng Lee ,  Da Jin ,  David Vigar

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/7854 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

摘要翻译： 形成具有圆形有源区域以提高GOI和漏电流控制的双门控晶体管的方法尤其包括以下步骤。 图案化SOI衬底，并且在图案化的上SOI硅层的暴露侧壁上形成圆形氧化物层。 在暴露的图案化的顶部氧化物层和上部SOI硅层的暴露部分之上形成具有限定栅极的开口的虚设层。 在底切下面的SOI氧化物层中形成底切，去除氧化物层的暴露的栅极区域部分。 去除栅极区域内的圆形氧化物层的部分，并且在该结构的一部分上形成共形氧化物层。 在第二图案化虚拟层开口内形成栅极，去除图案化虚拟层以形成双门控晶体管。