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    METHOD TO ENHANCE DEVICE PERFORMANCE WITH SELECTIVE STRESS RELIEF
    1.
    发明申请
    METHOD TO ENHANCE DEVICE PERFORMANCE WITH SELECTIVE STRESS RELIEF 有权
    增强选择性应力消除装置性能的方法

    公开(公告)号：US20080050868A1

    公开(公告)日：2008-02-28

    申请号：US11930230

    申请日：2007-10-31

    申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

    摘要翻译： 在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。 在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。 应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。 在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

    Method to enhance device performance with selective stress relief
    2.
    发明授权
    Method to enhance device performance with selective stress relief 有权

    公开(公告)号：US07309637B2

    公开(公告)日：2007-12-18

    申请号：US11299542

    申请日：2005-12-12

    申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

    Structure and method to implement dual stressor layers with improved silicide control
    3.
    发明申请
    Structure and method to implement dual stressor layers with improved silicide control 审中-公开
    具有改进的硅化物控制的双应力层的结构和方法

    公开(公告)号：US20080026523A1

    公开(公告)日：2008-01-31

    申请号：US11495508

    申请日：2006-07-28

    申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan ,  Eng Hua Lim

    发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan ,  Eng Hua Lim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

    摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.

    摘要翻译： 用于制造半导体器件的方法的示例实施例包括以下。 我们提供具有第一器件区域和第二器件区域的衬底。 我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。 我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。 第一应力层在第一器件区域中的衬底上施加第一类应力。 我们在第二设备区域上形成第二应力层。 第二应力层在第二器件区域中的衬底上施加第二类应力。 另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。

    Method to enhance device performance with selective stress relief
    4.
    发明授权
    Method to enhance device performance with selective stress relief 有权
    通过选择性应力消除来增强设备性能的方法

    公开(公告)号：US07659174B2

    公开(公告)日：2010-02-09

    申请号：US11930230

    申请日：2007-10-31

    申请人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    发明人： Yong Meng Lee ,  Haining S. Yang ,  Victor Chan

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

    摘要翻译： 在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。 在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。 应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。 在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

    THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER
    5.
    发明申请
    THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
    使用荧光植入和调整氧化层的阈值电压改进

    公开(公告)号：US20100289088A1

    公开(公告)日：2010-11-18

    申请号：US12465908

    申请日：2009-05-14

    申请人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    发明人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    IPC分类号： H01L27/088 ,  H01L21/8236

    CPC分类号： H01L21/823807

    摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

    摘要翻译： 可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。 形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。 将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。 在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。 外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

    Post-silicide spacer removal
    8.
    发明授权
    Post-silicide spacer removal 失效
    后硅化物间隔物去除

    公开(公告)号：US07393746B2

    公开(公告)日：2008-07-01

    申请号：US11548870

    申请日：2006-10-12

    申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

    发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

    IPC分类号： H01L21/33

    CPC分类号： H01L21/32 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

    摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

    摘要翻译： 一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。 然后，该方法在衬底的暴露区域的表面上形成硅化物。 该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。 接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。 随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。 该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。 由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

    Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance
    10.
    发明授权
    Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance 有权
    形成具有降低的栅 - 源 - 重叠电容的双栅绝缘体（SOI）晶体管的方法

    公开(公告)号：US06787404B1

    公开(公告)日：2004-09-07

    申请号：US10664262

    申请日：2003-09-17

    申请人： Yong Meng Lee ,  Da Jin ,  David Vigar

    发明人： Yong Meng Lee ,  Da Jin ,  David Vigar

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/78648

    摘要： A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer. A conformal oxide layer is formed around the channel portion of the patterned SOI silicon layer. A gate is formed within the patterned dummy layer opening. The gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer. The patterned dummy layer is then removed to form the double-gated transistor.

    摘要翻译： 一种形成双门控晶体管的方法，包括以下顺序步骤。 提供了具有形成在其上的SOI结构的衬底。 SOI结构包括下部SOI氧化物层和上部SOI硅层。 图案化SOI硅层以形成图案化SOI硅层，其包括通过沟道部分连接的源极区域和漏极区域。 在图案化SOI硅层上形成包围氧化物层，以形成被封装的图案化SOI硅层。 在封装的图案化SOI硅层上形成图案化虚拟层。 具有开口的图案化虚拟层具有暴露的侧壁，暴露：被封装的图案化SOI硅层的沟道部分; 以及SOI氧化物层的上表面的部分。 偏移间隔物在图案化虚拟层开口的暴露的侧壁上方。 蚀刻SOI氧化物层，同时最小化SOI氧化物层的上表面的底切部分被切入SOI氧化物层中以形成最小的底切。 最小化底切工艺也去除了图案化SOI硅层的通道部分上的偏移间隔物和包围氧化物层。 在图案化SOI硅层的沟道部分周围形成保形氧化物层。 在图案化虚拟层开口内形成栅极。 栅极包括在图案化SOI硅层上方的上栅极和在图案化SOI硅层下方的下栅极。 然后去除图案化的虚拟层以形成双门控晶体管。