NOVEL SOLID FORMS OF A MICROBIOCIDE
    42.
    发明申请
    NOVEL SOLID FORMS OF A MICROBIOCIDE 有权
    微生物的新型固体形式

    公开(公告)号:US20130203832A1

    公开(公告)日:2013-08-08

    申请号:US12531503

    申请日:2008-02-19

    IPC分类号: C07D231/14 A01N43/56

    CPC分类号: C07D231/14 A01N43/56

    摘要: The present invention relates to novel solid forms of 3-difluoromethyl-1-methyl-1H-pyrazole-4-carboxylic acid (9-isopropyl-1,2,3,4-tetrahydro-1,4-methano-naphthalen-5-yl)-amide, such as crystal modifications and hydrates, compositions comprising these novel solid forms and to the use thereof in the control of disease infestation in cultivated plants.

    摘要翻译: 本发明涉及新型固体形式的3-二氟甲基-1-甲基-1H-吡唑-4-羧酸(9-异丙基-1,2,3,4-四氢-1,4-亚甲基 - 萘-5-基) 吡啶基) - 酰胺,例如晶体修饰物和水合物,包含这些新型固体形式的组合物及其在控制栽培植物中疾病侵袭的用途。

    Biocide Compositions for Use in Coatings
    44.
    发明申请
    Biocide Compositions for Use in Coatings 有权
    用于涂料的杀菌剂组合物

    公开(公告)号:US20090145327A1

    公开(公告)日:2009-06-11

    申请号:US12331932

    申请日:2008-12-10

    IPC分类号: A01N59/16 C09D7/00 A01N25/08

    摘要: Biocide compositions capable of increasing the fading resistance of a coating material, which compositions preferably comprise a nano-sized halogenated benzonitrile and a nano-sized zinc oxide, are disclosed. Coating compositions, which comprise the biocide compositions, binders, and pigments are disclosed. The biocide compositions are particularly suitable for use in paints. Methods for reducing the fading of pigmented coating compositions upon exposure to light are also disclosed.

    摘要翻译: 公开了能够提高涂料的抗褪色性的杀生物剂组合物,该组合物优选包含纳米尺度的卤代苄腈和纳米尺寸的氧化锌。 公开了包含杀生物剂组合物,粘合剂和颜料的涂料组合物。 杀生物剂组合物特别适用于涂料。 还公开了降低着色涂料组合物在光照下的褪色的方法。

    Self-regulating hydrogen generator
    45.
    发明授权
    Self-regulating hydrogen generator 失效
    自调氢发生器

    公开(公告)号:US06939529B2

    公开(公告)日:2005-09-06

    申请号:US10264302

    申请日:2002-10-03

    摘要: A hydrogen generating system regulates its rate of hydrogen generation by monitoring one or more parameters of the hydrogen generation process and then providing relative movement between the fuel tank and the catalyst chamber so as to increase or decrease the rate of hydrogen generation.In the disclosed embodiments, the catalyst chamber is disposed in a tank containing the fuel. The relative movement provided moves the catalyst chamber toward the fuel solution so as to increase the rate of hydrogen generation and moves the catalyst chamber away from the fuel solution to decrease such generation. Advantageously, such self-regulation can be provided without an external power source and can be varied to meet the requirements of different commercial applications. The overall system can be readily fabricated using commercially available parts.

    摘要翻译: 氢气发生系统通过监测氢气产生过程的一个或多个参数并且然后在燃料箱和催化剂室之间提供相对运动来调节其产生氢气的速率,以便增加或降低生成氢气的速率。 在所公开的实施例中,催化剂室设置在容纳燃料的罐中。 提供的相对运动将催化剂室朝向燃料溶液移动,以便增加氢的产生速率并使催化剂室远离燃料溶液以减少这种产生。 有利地,可以在没有外部电源的情况下提供这种自调节,并且可以改变以满足不同商业应用的要求。 可以使用市售零件容易地制造整个系统。

    Use of fatty acid esters based on fatty acids containing alicyclic structural elements as solvents for printing inks
    46.
    发明申请
    Use of fatty acid esters based on fatty acids containing alicyclic structural elements as solvents for printing inks 审中-公开
    使用基于脂肪酸脂肪酸脂肪酸酯的脂肪酸酯作为印刷油墨的溶剂

    公开(公告)号:US20050120909A1

    公开(公告)日:2005-06-09

    申请号:US10952117

    申请日:2004-09-28

    CPC分类号: C09D11/033

    摘要: Fatty acid esters of which the fatty acid constituents are saturated and/or mono- or polyolefinically unsaturated fatty acids containing a total of 12 to 22 carbon atoms and of which the alcohol constituents are saturated and/or mono- or polyolefinically unsaturated monoalcohols containing a total of 1 to 22 carbon atoms, with the additional proviso that the fatty acid constituents of the esters contain an alicyclic group which may optionally be substituted by an aliphatic group, are suitable as solvents for printing inks.

    摘要翻译: 脂肪酸组分是饱和脂肪酸酯和/或含有总共12-22个碳原子的单 - 或聚烯烃不饱和脂肪酸,其中醇成分是饱和的和/或含有总量的单 - 或聚烯烃不饱和一元醇 具有1至22个碳原子,另外条件是酯的脂肪酸组分含有可任选被脂族基团取代的脂环基,适用作印刷油墨的溶剂。

    Apparatus and method for generating a pulse signal
    48.
    发明授权
    Apparatus and method for generating a pulse signal 有权
    用于产生脉冲信号的装置和方法

    公开(公告)号:US06222393B1

    公开(公告)日:2001-04-24

    申请号:US09357474

    申请日:1999-07-20

    IPC分类号: H03K500

    CPC分类号: H03K5/1534 H03K2005/00293

    摘要: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

    摘要翻译: 一种用于响应于输入信号产生脉冲信号的电路。 该电路为脉冲信号提供脉冲宽度。 第一逻辑装置接收输入信号并产生第一中间信号。 延迟装置耦合到第一逻辑装置并且接收第一中间信号。 延迟装置在一段时间后响应于第一中间信号产生第二中间信号。 第二中间信号具有与第二中间信号相同的状态。 第二逻辑器件耦合到第一逻辑器件和延迟器件。 第二逻辑装置响应于第一中间信号产生脉冲信号。

    Apparatus and method for generating a pulse signal
    49.
    发明授权
    Apparatus and method for generating a pulse signal 失效
    用于产生脉冲信号的装置和方法

    公开(公告)号:US5933032A

    公开(公告)日:1999-08-03

    申请号:US897375

    申请日:1997-07-21

    IPC分类号: H03K5/06 H03K5/153 H03K5/00

    CPC分类号: H03K5/153 H03K5/06

    摘要: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

    摘要翻译: 一种用于响应于输入信号产生脉冲信号的电路。 电路为脉冲信号提供脉冲宽度。 第一逻辑装置接收输入信号并产生第一中间信号。 延迟装置耦合到第一逻辑装置并且接收第一中间信号。 延迟装置在一段时间后响应于第一中间信号产生第二中间信号。 第二中间信号具有与第二中间信号相同的状态。 第二逻辑器件耦合到第一逻辑器件和延迟器件。 第二逻辑装置响应于第一中间信号产生脉冲信号。

    Method and apparatus for reducing skew among input signals within an
integrated circuit
    50.
    发明授权
    Method and apparatus for reducing skew among input signals within an integrated circuit 失效
    用于减少集成电路内的输入信号之间的偏差的方法和装置

    公开(公告)号:US5903174A

    公开(公告)日:1999-05-11

    申请号:US575554

    申请日:1995-12-20

    CPC分类号: H03K19/00323 H03K19/0013

    摘要: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices. The additional PMOS device acts as a choke on the current flow through the pair of parallel PMOS devices thereby reducing propagation delay differences which would otherwise occur as a result of either only one or both of the parallel PMOS devices operating to pull up the output path. Similar circuit modifications are provided within NOR gates or logic gates.

    摘要翻译: 集成电路包括具有地址路径的输入路径电路,该地址路径具有用于向寄存器提供地址信号的输入缓冲器。 具有输入缓冲器的单独的时钟路径提供用于对寄存器计时的时钟信号。 输入路径电路还包括一个或多个解码单元,每个解码单元具有多个逻辑门单元,例如NAND门单元或NOR门单元。 在逻辑门内提供电路,用于通过逻辑门减少诸如地址信号的多位二进制信号的传播之间的定时延迟差异。 在这里描述的示例性NAND门中,定时延迟差异的减小通过沿着电源和输出路径之间的电流路径定位另外的PMOS器件来实现,否则仅包括一对并联PMOS器件。 附加的PMOS器件用作通过该对并联PMOS器件的电流的扼流圈,从而减少由于只有一个或两个并联PMOS器件工作以上拉输出路径而导致的传播延迟差异。 在NOR门或逻辑门内提供类似的电路修改。