Secure Flash Controller
    42.
    发明公开

    公开(公告)号:US20230274037A1

    公开(公告)日:2023-08-31

    申请号:US18309851

    申请日:2023-05-01

    CPC classification number: G06F21/79 G06F21/602 G06F12/1441

    Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is to communicate with an NVM. The processor is to store in the NVM at least a Type-Length-Value (TLV) record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least a validity indicator of the TLV record, to read the TLV record from the NVM, and to invalidate the TLV record by modifying the validity indicator stored in the non-encrypted fields, without decryption of any of the encrypted fields.

    Secure flash controller
    43.
    发明授权

    公开(公告)号:US11681635B2

    公开(公告)日:2023-06-20

    申请号:US17013693

    申请日:2020-09-07

    CPC classification number: G06F12/1408 G06F12/0246 G06F12/0891 G06F21/79

    Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

    UNIDIRECTIONAL COUNTER
    44.
    发明申请

    公开(公告)号:US20220382868A1

    公开(公告)日:2022-12-01

    申请号:US17336123

    申请日:2021-06-01

    Abstract: Apparatuses, systems, and techniques that implement a unidirectional counter with one-time-programmable memory that prevents the counter from reversing direction. In at least one embodiment, a unidirectional counter is implemented with a base value represented as a binary number and an offset represented as a bit field where each bit represents an equal amount.

    Physical hardware clock chaining
    46.
    发明授权

    公开(公告)号:US11070304B1

    公开(公告)日:2021-07-20

    申请号:US16799873

    申请日:2020-02-25

    Abstract: In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.

    Support of Option-ROM in socket-direct network adapters

    公开(公告)号:US10318312B2

    公开(公告)日:2019-06-11

    申请号:US15717969

    申请日:2017-09-28

    Abstract: A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that belong to a multi-CPU device. The processor is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, and, in response to a request from the multi-CPU device to report the support of the Option-ROM functionality, to report the support of the Option-ROM functionality over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device.

    Multi-host network interface controller with host management

    公开(公告)号:US10148746B2

    公开(公告)日:2018-12-04

    申请号:US14583124

    申请日:2014-12-25

    Abstract: A network adapter includes one or more ports and circuitry. The ports are configured to connect to a switch in a communication network. The circuitry is coupled to a network node that includes multiple hosts, and is configured to exchange management packets between a control server and multiple BMC units associated respectively with the multiple hosts, and to exchange, over the communication network via the one or more ports, data packets between the hosts and one or more remote nodes.

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