公开(公告)号：US20200176067A1

公开(公告)日：2020-06-04

申请号：US16787199

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/04

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US20200034223A1

公开(公告)日：2020-01-30

申请号：US16049439

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli ,  Scott Anthony Stoller

IPC: G06F11/07

Abstract: Aspects of the present disclosure include accessing block data stored in a memory component including memory blocks. The block data identifies bad blocks and reusable bad blocks, the reusable bad blocks having a higher level of reliability than bad blocks. Block selection is performed to select a block based on a block address. Based on the block selection and based on the block data, a tag operation is performed by setting a latch of the selected block to a first state in which access to the selected block is disabled.

公开(公告)号：US20250044970A1

公开(公告)日：2025-02-06

申请号：US18797447

申请日：2024-08-07

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Anna Scalesse ,  Iolanda Del Villano ,  Maddalena Calzolari ,  Chiara Cerafogli ,  Carla L. Christensen

IPC: G06F3/06

Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

公开(公告)号：US20250014665A1

公开(公告)日：2025-01-09

申请号：US18759105

申请日：2024-06-28

Applicant: Micron Technology, Inc.

Inventor： Ivo Thomas Wambeke ,  James Eric Davis ,  Joshua Daniel Tomayer ,  Fulvio Rori ,  Chiara Cerafogli ,  Kenneth William Marr

IPC: G11C29/32 ,  G11C29/12 ,  G11C29/42

Abstract: A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.

公开(公告)号：US12189522B2

公开(公告)日：2025-01-07

申请号：US17853219

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Justin Bates ,  Ryan Hrinya ,  Fulvio Rori ,  Chiara Cerafogli ,  Carmine Miccoli

IPC: G06F12/02

Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

公开(公告)号：US12073100B2

公开(公告)日：2024-08-27

申请号：US17663137

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Anna Scalesse ,  Iolanda Del Villano ,  Maddalena Calzolari ,  Chiara Cerafogli ,  Carla L. Christensen

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

公开(公告)号：US20240233839A9

公开(公告)日：2024-07-11

申请号：US18489770

申请日：2023-10-18

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Marco Domenico Tiburzi ,  Matthew Joseph Iriondo ,  Warren Lee Boyer ,  Brian James Soderling ,  James Eric Davis ,  Fulvio Rori

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G01K13/00

Abstract: A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.

公开(公告)号：US20240136000A1

公开(公告)日：2024-04-25

申请号：US18489770

申请日：2023-10-17

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Marco Domenico Tiburzi ,  Matthew Joseph Iriondo ,  Warren Lee Boyer ,  Brian James Soderling ,  James Eric Davis ,  Fulvio Rori

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G01K13/00

Abstract: A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.

公开(公告)号：US20240045914A1

公开(公告)日：2024-02-08

申请号：US18223931

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Jonathan S. Parry

IPC: G06F16/9535 ,  G06F16/9538

CPC classification number: G06F16/9535 ,  G06F16/9538

Abstract: Processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. The processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.

公开(公告)号：US11797192B2

公开(公告)日：2023-10-24

申请号：US17236183

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Carly M. Wantulok ,  Sumana Adusumilli ,  Chiara Cerafogli

IPC: G06F3/06 ,  G06N20/00

CPC classification number: G06F3/0619 ,  G06F3/067 ,  G06F3/0623 ,  G06F3/0656 ,  G06F3/0659 ,  G06N20/00

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.