公开(公告)号：US11823743B2

公开(公告)日：2023-11-21

申请号：US17747516

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/04 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/20 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US11817145B2

公开(公告)日：2023-11-14

申请号：US17691684

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan W. Oh ,  Fulvio Rori

IPC: G11C16/04 ,  G11C11/56

CPC classification number: G11C11/5671 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

Abstract: Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.

公开(公告)号：US20230360708A1

公开(公告)日：2023-11-09

申请号：US17739789

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Jiun-Horng Lai ,  Ching-Huang Lu ,  Fulvio Rori ,  Wai Ying Lo ,  Scott A. Stoller

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/3445

Abstract: Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

公开(公告)号：US11681474B2

公开(公告)日：2023-06-20

申请号：US17562590

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F1/14

CPC classification number: G06F3/0659 ,  G06F1/14 ,  G06F3/0604 ,  G06F3/0673 ,  G11C7/1009

Abstract: A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

公开(公告)号：US11567688B2

公开(公告)日：2023-01-31

申请号：US17122484

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Giuseppe Cariello

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C16/34 ,  G11C16/16

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20220343985A1

公开(公告)日：2022-10-27

申请号：US17238818

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Kishore Kumar Muchherla ,  Fulvio Rori ,  Bin Wang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

公开(公告)号：US20220121399A1

公开(公告)日：2022-04-21

申请号：US17562590

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/06 ,  G06F1/14 ,  G11C7/10

Abstract: A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

公开(公告)号：US11170860B2

公开(公告)日：2021-11-09

申请号：US16787199

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32 ,  G11C16/16 ,  G11C11/56

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US20210193199A1

公开(公告)日：2021-06-24

申请号：US16946305

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Jonathan Wen Jian Oh ,  Aaron James Olson ,  Fulvio Rori ,  Qisong Lin ,  Preston A. Thomson

IPC: G11C7/10 ,  G06F9/30 ,  G06F11/27 ,  G06F12/0882

Abstract: A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.

公开(公告)号：US20210042037A1

公开(公告)日：2021-02-11

申请号：US16532357

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.