公开(公告)号：US11275650B2

公开(公告)日：2022-03-15

申请号：US17038251

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/4063 ,  G11C11/4076 ,  G11C29/52 ,  G11C7/22 ,  G11C7/10 ,  G11C29/04 ,  G11C8/12

Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

公开(公告)号：US20220068349A1

公开(公告)日：2022-03-03

申请号：US17005034

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

公开(公告)号：US20220013156A1

公开(公告)日：2022-01-13

申请号：US17486481

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US20210394339A1

公开(公告)日：2021-12-23

申请号：US17409495

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: B24D18/00 ,  E21B10/567 ,  B32B3/30 ,  E21B10/573 ,  B32B13/06

Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

公开(公告)号：US20210173557A1

公开(公告)日：2021-06-10

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US11031083B2

公开(公告)日：2021-06-08

申请号：US16249714

申请日：2019-01-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary L. Howe ,  Scott E. Smith

IPC: G11C8/00 ,  G11C16/08 ,  G11C7/06 ,  G11C8/10

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

公开(公告)号：US10783968B2

公开(公告)日：2020-09-22

申请号：US16520071

申请日：2019-07-23

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe

IPC: G11C7/00 ,  G11C16/08 ,  G11C11/406 ,  G11C11/16 ,  G11C5/06 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/408

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

公开(公告)号：US10534553B2

公开(公告)日：2020-01-14

申请号：US15691484

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US10510398B2

公开(公告)日：2019-12-17

申请号：US15826236

申请日：2017-11-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US10403364B2

公开(公告)日：2019-09-03

申请号：US16110992

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe

IPC: G11C7/00 ,  G11C16/08 ,  G11C11/406 ,  G11C11/16 ,  G11C5/06 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/408

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.